HPS Address Space and HPS2FPGA axi bridge

[Altera_Forum]

Hi, 

 I am using the Arrow C5 SoC Kit. This kit has 1GB of ddr3 connected on both the FPGA side and the HPS side.   I am trying to make the 1GB on the FPGA side visible in the HPS.   I have created a QSYS system that instantiates the DDR3 SDRAM Controller with UniPHY which has an address range of 0x0000_0000 to 0x3FFF_FFFF. I have instantiated a Hard processor System with a 32 bit data width HPS2FPGA bridge and a 32 bit LWHPS2FPGA bridge. I have connected the ddr3 controller to the h2f_axi_master. see attached image qsys.  The documentation for the HPS Technical Reference Manual and some examples/tutorials state that the start address of the h2f_axi_master is 0xC000_0000. Using the table for address space relationship on the MPU (see attached) and the table for common address space regions (see attached) the h2f_axi_master is using the FPGA Slaves Region which starts at address 0xC000_0000 to 0xFC00_0000 which is 960MB. Everything from 0xFC00_0000 up is used for peripherals etc.   My Questions:  1) The MPU has an address space range of 4GB, how can I change where the start address for the h2f_axi_master starts so I can access the full range of the DDR3 and hopefully add some other interfaces on.  2) in qsys if I string anything else onto the h2f_axi_master bus it starts to complain about addresses being out of range. How can I change this? It seems strange to me that if there is actually only 960MB of accessible space and im sticking 1GB on the bus, shouldn't QSYS kick up an error?  3) There is over 2GB of "SDRAM Window" address space on the MPU I don't understand how to access this or make it visible to a bus.   4) I have looked at the address span extender component but it doesn't make much sense to me when I add it to the QSYS. If I was to use the address span extender how would I access the memory space on my HPS. At the moment I open a fd and mmap the virtual address space with an offset and a span. Will the address space extender still start at 0xC000_0000?   Any help would be really great!!  Thanks  James

[Altera_Forum]

#1 You can't move the location of the H2F bridge, the HPS is an ASIC so you can't move the base addresses around like soft logic in Qsys. The only way to address more than 960MB of address space on the other side of the H2F bridge is to include the address span expander in the Qsys system and page the memory. 

# 2 Qsys has no idea that the HPS can only address 960MB of memory from the H2F bridge master port. This is a limitation of the HPS. The only thing I could see being feasible is for the HPS component to issue the warning by querying Qsys to tell it how much memory is connected to the master then error out if it exceeds 960MB. That said I think I would be annoyed if I saw that message after hooking up 1GB of SDRAM to that bridge since I would be ok with not making 64MB of that memory directly accessible to the HPS. If I had logic in the FPGA that needs access to the same memory that 64MB at the end that is not directly accessible to the HPS can still be accessed by logic in the FPGA. # 3 In the L2 cache there is a programmable window that determines whether transactions route to the L3 interconnect (M0) or to the SDRAM (M1). The window sets the start and end address (in 1MB chunks) a range that gets routed to the SDRAM. For example if I want the MPU have 3GB of HPS SDRAM visible to it I would set the start at address 0x0 and the end to 0xC000_0000. That means any time either processor accesses addresses in the lower 3GB of the address space they all will be routed to the SDRAM instead of the L3 interconnect. The HPS MPU chapter describes this mechanism in more detail. # 4 If I understood the question correct, when you access the HPS memory space from the FPGA it's exposed as a full 4GB through the F2H bridge. The reason why you see this connection paired with an address span expander is if your master in the FPGA only supports a 4GB address space, connecting it directly to the HPS will prevent it from being connected to anything else (you used up it's full 4GB address space on the HPS connection). So the address span expander let's you implement a paging system to minimize how much address span is downstream from the master connected to it. For example if I wanted Nios II to be able to access the 4GB HPS address space I might setup the address span expander to have a 128MB window that I can move around so that Nios II only has access to a 128MB page into the total 4GB address space inside the HPS. That's why I was saying for# 1 you could use a similar technical to expand the addressing capabilities of the H2F bridge. Keep in mind you have to maintain the address span extender window in software and it's not a good idea to move that window when there are outstanding transactions.

[Altera_Forum]

--- Quote Start ---  #1 You can't move the location of the H2F bridge, the HPS is an ASIC so you can't move the base addresses around like soft logic in Qsys. The only way to address more than 960MB of address space on the other side of the H2F bridge is to include the address span expander in the Qsys system and page the memory.  # 2 Qsys has no idea that the HPS can only address 960MB of memory from the H2F bridge master port. This is a limitation of the HPS. The only thing I could see being feasible is for the HPS component to issue the warning by querying Qsys to tell it how much memory is connected to the master then error out if it exceeds 960MB. That said I think I would be annoyed if I saw that message after hooking up 1GB of SDRAM to that bridge since I would be ok with not making 64MB of that memory directly accessible to the HPS. If I had logic in the FPGA that needs access to the same memory that 64MB at the end that is not directly accessible to the HPS can still be accessed by logic in the FPGA.  # 3 In the L2 cache there is a programmable window that determines whether transactions route to the L3 interconnect (M0) or to the SDRAM (M1). The window sets the start and end address (in 1MB chunks) a range that gets routed to the SDRAM. For example if I want the MPU have 3GB of HPS SDRAM visible to it I would set the start at address 0x0 and the end to 0xC000_0000. That means any time either processor accesses addresses in the lower 3GB of the address space they all will be routed to the SDRAM instead of the L3 interconnect. The HPS MPU chapter describes this mechanism in more detail.  # 4 If I understood the question correct, when you access the HPS memory space from the FPGA it's exposed as a full 4GB through the F2H bridge. The reason why you see this connection paired with an address span expander is if your master in the FPGA only supports a 4GB address space, connecting it directly to the HPS will prevent it from being connected to anything else (you used up it's full 4GB address space on the HPS connection). So the address span expander let's you implement a paging system to minimize how much address span is downstream from the master connected to it. For example if I wanted Nios II to be able to access the 4GB HPS address space I might setup the address span expander to have a 128MB window that I can move around so that Nios II only has access to a 128MB page into the total 4GB address space inside the HPS. That's why I was saying for# 1 you could use a similar technical to expand the addressing capabilities of the H2F bridge. Keep in mind you have to maintain the address span extender window in software and it's not a good idea to move that window when there are outstanding transactions.[/QUOTE   Dear badOmen  I use cycone V board with 2GB sdram, i cofigure the preloader and u-boot to have 2GB sdram also. I cant write with memtool to address from 0x80000000 to 0xc0000000 - i have error massage   root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/hps2fpga/enable root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/fpga2hps/enable root@socfpga_cyclone5:~# memtool -32 0x80000000=0x00200100 Writing 32-bit value 0x200100 to address 0x80000000 [ 6839.386707] Unhandled fault: external abort on non-linefetch (0x1818) at 0x76fd3000 Bus error   and i know it is related to preloader only (if i use older preloader - 13.1 it works O.K) how can i set the start address and end address as mentioned before at q3. i use quartus 14.1 or 15.0 and with both i have the same error  thanks a lot  yehuda

[Altera_Forum]

dear badOman 

 I have cyclone V custom board with 2G sdram configured with Qsys 14.1.  my problem is when i try to write with memtool to address from 0x80000000 to 0xc0000000 i get error massage  root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable  root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/hps2fpga/enable  root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/fpga2hps/enable  root@socfpga_cyclone5:~# memtool -32 0x80000000=0x00200100  Writing 32-bit value 0x200100 to address 0x80000000  [ 6879.506640] Unhandled fault: external abort on non-linefetch (0x1818) at 0x76fe9000  Bus error  root@socfpga_cyclone5:~#   i do open the bgidges but it looks like the kernel cant see the memory region 0x80000000 to 0xc0000000 i know it is related to the preloader since when i use preloader generated with quartus 13.1 i dont have that problem  as mentioned on# 3 before can you give some more dtails how to configure the hps to be exposed to 3GB sdram    thanks  yehuda otzri

[Altera_Forum]

dear badOman 

    I have cyclone V custom board with 2G sdram configured with Qsys.  my problem is when i try to write with memtool to address from 0x80000000 to 0xc0000000 i get error massage  root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable  root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/hps2fpga/enable  root@socfpga_cyclone5:~# echo 1 > /sys/class/fpga-bridge/fpga2hps/enable  root@socfpga_cyclone5:~# memtool -32 0x80000000=0x00200100  Writing 32-bit value 0x200100 to address 0x80000000  [ 6879.506640] Unhandled fault: external abort on non-linefetch (0x1818) at 0x76fe9000  Bus error  root@socfpga_cyclone5:~#  i do open the bgidges but it looks like the kernel cant see the memory region 0x80000000 to 0xc0000000 i know it is related to the preloader - when i use quartus 13.1 it is o.k and when i use quartus 14.1 or 15.0 i get the error massage as mentioned on# 3 before can you give some more dtails how to configure the hps to be exposed to 3GB sdram    thanks yehuda otzri

[Altera_Forum]

you will probably have more luck starting a new thread with a full explanation of your problem rather than tagging onto the end of another similar problem.