HPS BareMetal EMAC driver

[Altera_Forum]

hey guys, 

 I have been trying with no success to write a driver for the HPS EMAC for my baremetal application.  I looked at the designware.c at the U BOOT as a ref.   first of all I connect the board to my PC and saw that auto negotiation end successfully.  I am able to use the MDIO channel and varify its ok (furthermore the SGMII_RGMII_SMII_Control_Status shows 1Gig full duplex ) so I assumed that the PHY is ok.  so I configured the MAC and the DMA with the following options :   DMA:  bus mode register  1. FIXEDBURST  2. PBL = 16 opmode  1.FLUSH TX FIFO  2.store & forward  3.Processes second frame  MAC :  1. full duplex  2. MAC address 111111111111  3. promiscuous mode  set the descriptors list to the appropriate register. and lunched the dma( verified throw current descriptor & buffer registers that they are locked on the right addresses and that the DMA is in idle state) then afterwards enabled the MAC.   built frame(150 byte big) and copied it to the current descriptor buffer. set the OWNBYDMA , LAST FRAME, FIRST FRAME bit and lunched the dma by using txpolldemand. the DMA release the decriptor by clearing the OWNBYDMA but no packet transmited.  furthermore I see clearly that packets are entering the PHY all the MAC counters are zeros and the MAC debug regiester is always empty( the rx mac state machine is enabled)

[Altera_Forum]

May you try Ethernet without DMA ? Because big promlems may be there. 

In Baremetal no ashame to direct write bytes to MAC and read back ! :)

[Altera_Forum]

--- Quote Start ---  hey guys,  I have been trying with no success to write a driver for the HPS EMAC for my baremetal application.  I looked at the designware.c at the U BOOT as a ref.   first of all I connect the board to my PC and saw that auto negotiation end successfully.  I am able to use the MDIO channel and varify its ok (furthermore the SGMII_RGMII_SMII_Control_Status shows 1Gig full duplex ) so I assumed that the PHY is ok.  so I configured the MAC and the DMA with the following options :   DMA:  bus mode register  1. FIXEDBURST  2. PBL = 16 opmode  1.FLUSH TX FIFO  2.store & forward  3.Processes second frame  MAC :  1. full duplex  2. MAC address 111111111111  3. promiscuous mode  set the descriptors list to the appropriate register. and lunched the dma( verified throw current descriptor & buffer registers that they are locked on the right addresses and that the DMA is in idle state) then afterwards enabled the MAC.   built frame(150 byte big) and copied it to the current descriptor buffer. set the OWNBYDMA , LAST FRAME, FIRST FRAME bit and lunched the dma by using txpolldemand. the DMA release the decriptor by clearing the OWNBYDMA but no packet transmited.  furthermore I see clearly that packets are entering the PHY all the MAC counters are zeros and the MAC debug regiester is always empty( the rx mac state machine is enabled)  --- Quote End ---    I wrote an driver for the HPS EMAC for my baremetal application and it is working fine. I also worked with the designware.c as reference but i looked also in the datasheet sheet from altera cv_5v4.pdf there is explained what you have to do for initialization and more. Please contact me at hinn@hinn.de if you need more help.

[Altera_Forum]

hey arkadish123, 

 have you managed to resolve your problem? I'm facing the exact same problem, auto negotiation end successfully, but I fail to send/receive packets.