Using the Cyclone V SoC chipset I am currently having an issue with regards to seeing a HPS LOAN IO input coming back to the fabric of the FPGA.
I am having difficulties reading the signal in a register from a custom SPI Core I have built. The simulation is working and it is attached to the correct LOAN IO and pin is set to an input in the VHDL code; so everything is set correctly. I am trying to use the system console to read from a memory register that is capturing an input from the HPS LOAN IO. Even though the signal is present on the scope HPS side no signals are being sampled into the register. Could you advise? Kyle