HPS vs FPGA configuration

[Altera_Forum]

I am confused about the HPS configuration. Specifically in a Cyclone V device. 

 The peripherals for the ARM CPU can be configured under Qsys, including SDRAM, UARTs, the SD card interface, etc. This would imply that the FPGA would need to be configured before the ARM CPU could operate.  But the ARM can configure the FPGA. So there seems to be a "chicken and egg" situation here: which comes first?  Does the HPS have a "default" configuration that would allow booting from SD card and then configure the FPGA?   If so, at what point in the process do the I/O pins change from their default to the configuration established by Qsys?  Rod

[Altera_Forum]

Hi Rod, 

 The FPGA fabric and HPS in the SoC FPGA must be powered at the same time. You can reduce the clock frequencies or gate the clocks to reduce dynamic power. Once powered, the FPGA fabric and HPS can be configured independently thus providing you with more design flexibility:  • You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the board through the FPGA configuration controller. • configure the fpga fabric first, and then boot the hps from memory accessible to the fpga fabric.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Anand: 

  I am powering all the Cyclone together. We have no need for reduced power settings so that is not an issue.  What I am not understanding is how the various options of the HPS system get configured. If I am understanding it correctly, the HPS can operate before the FPGA portion has been configured. If so, it must be operating in some default condition.  Our board has been designed with a serial configuration FLASH prom for configuring the FPGA, so whatever the requirements are I am sure we can meet them. But there has been discussion among the engineers regarding the need for the serial FLASH (EPCQ128). Ultimately we want to be able to re-configure the FPGA portion via the HPS for remote update capability. So if the Serial FLASH prom is not needed we can eliminate it and save $30.  But I am still confused on the HPS configuration. Using the Qsys tools I specified the type of DRAM I was using and chose options for serial ports. These selections can't be applied until the FPGA configuration image is loaded.   So how does the ARM boot if configuration information hasn't been loaded yet?  Is there a default that is guaranteed to work?  Rod

[Altera_Forum]

No indeed, the options you set in QSys for the DRAM and other HPS parameters aren't actually compiled in the FPGA image, but are used when you generate the preloader. It is the preloader that will configure the HPS part. Just remember to regenerate and reflash the preloader each time you change those parameters. 

The default HPS mode is set with the dedicated pins (clock select, boot select, and maybe other ones, I don't remember) and this default mode is just enough to load the preloader into the internal SRAM and start it.