HVIO and HSIO inputs during power-up

[AlexKucherov]

Hello Intel Team

What should be the state of the HVIO and HSIO inputs during unpowered FPGA and power -up and power-down state? Is there any limitations?

If there is an issue if the peripheral device powered before the FPGA?

In AN 692: Power Sequencing Considerations for Cyclone® 10 GX,Arria® 10, Stratix® 10, Agilex™ 7, and Agilex™ 5 Devices

Agilex HVIO do not mention – see below

[JohnT_Intel]

Hi, 

you will need to refer to Agilex 7 General-Purpose IO User Guide https://cdrdv2-public.intel.com/768846/ug-683780-768846.pdf table 3.