Handle DMA Page address received at the FPGA end during DMA transfer

[Altera_Forum]

Scatter Gather DMA transfer of 461KB is initiated from the Host PC to the ARRIA2GX FPGA using Jungo Driver. 

 During the transfer apart from the actual data sent as input data , extra data which looks like set of Page address( Physical address ) which keeps varying all the time for ex :  0X0000000000020400(64bit) & 0X1cb2b00000000000(64bit)  0X0000000000020800(64bit) & 0X2b42600000000000(64bit) 0X0000000000020800(64bit) & 0X165df00000000000(64bit) 0X0000000000021400(64bit) & 0X2ccf500000000000(64bit) 0X0000000000022800(64bit) & 0X165df00000000000(64bit) 0X0000000000021800(64bit) & 0X6f2cd00000000000(64bit) 0X0000000000023400(64bit) & 0X325da00000000000(64bit) 0X0000000000024500(64bit) & 0X43ffc00000000000(64bit)  this keeps happening and due to the varying data this Page Address/wrong data is going to our module/design as a valid data and is creating problems to our design.  This RX port is of 64 bit width  Is there any way to handle or eliminate this data from being received at the rx port ??      More Info on IP generation  HARD IP is generated for  PHY type - ARRIAII GX lane - x1 port type - Native Endpoint Application Interface - Avalon ST 64bit PCI Express Version - 1.1 maximum payload - 256 desired performance for receiving request - MAXIMUM  BAR REGISTERS  Bar 0 - 32 bit non-prefetchable Bar 1 - 32 bit non-prefetchable Bar 2 - 32 bit non-prefetchable

[Altera_Forum]

I have no experience with PCI Express so I can't answer you directly, but this triggered my attention: 

--- Quote Start ---  Scatter Gather DMA transfer of 461KB  --- Quote End ---  are you transferring those with only one descriptor, or with a chain of descriptors? AFAIK the SGDMA core is limited to 64kb transfers, so if you try to transfer more than this amount with a single descriptor, you will probably run into strange results. Can you put a signaltap probe on the stream interface on the SGDMA to check that the data packets are transferred correctly?

[Altera_Forum]

We are using Chain of Descriptors. 

Explanation: Once the driver allocates a buffer of 461KBytes of data, the Operating system allocates pages (of 4KBytes in size). So 461KBytes of data is allocated with (461KBytes/4KBytes) number of pages/descriptors. the data size wont exceed 4 KB/descriptor (It can hold less than 4KBytes).  The data packet are received correctly with no mismatches but along with the data packets I get the extra packet as mentioned in the earlier post.

[Altera_Forum]

Then there shouldn't be any problem from the SGDMA itself. Did you try to use signaltap on the avalon stream to see if those packets are actually coming from the PCIex core of if it is something else? Are you using a Nios CPU in the FPGA to access the data? In that case are you bypassing the CPU's data cache when you read the packet contents?

[Altera_Forum]

Not using NIOS CPU to access data. NIOS CPU is used only to reset and start the module..!! Haven't tried looking into the avalon stream data. Will look into it.. :)

[Altera_Forum]

@Daixiwen : I Have checked on the avalon stream data.. Can find these data there also.

[Altera_Forum]

I suggest that you contact mySupport with your findings, hopefully they will be able to help you find out where they come from.