Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21611 Discussions

Having a clock issue

Altera_Forum
Honored Contributor II
2,099 Views

Im rather new to quartus and having trouble with one of my assignments. 

 

I am designing a moore counter using 8 states and 3 jkff2 flip flops. Im almost certain that everything is wired up correctly but my simulation only shows the first state and almost seems that the circuit is not running the positive edge clock input.  

 

Im not sure if i have to do anything to set up the clock or if simply creating an input with a controlled waveform is right but for some reason the clock won't shift into the second state. 

 

Any suggestions or help would be greatly appreciated. 

 

Thank you.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
1,078 Views

Have you got a testbench? why not post the code and the specific problems, maybe showing a waveform that shows the problem. Otherwise, we can only guess.

0 Kudos
Altera_Forum
Honored Contributor II
1,078 Views

Hi Eddywick 

 

Please post your sample piece of code about your state transitions so that we can find out why the state is stuck at first state itself
0 Kudos
Altera_Forum
Honored Contributor II
1,078 Views

I haven't had to code the assignment yet just using Block Diagram/Schematic File. Attached is the circuit

0 Kudos
Altera_Forum
Honored Contributor II
1,078 Views

The picture is too low resolution to reall read it properly. Please re-attach at a higher res.

0 Kudos
Altera_Forum
Honored Contributor II
1,078 Views

This might be better

0 Kudos
Reply