Please help a newbie, I've done everything I knew how to do and can't seem to solve this...
Doing some retro computer emulation with Verilog and Cyclone V FPGA to teach myself the basics. I've actually got it working OK, what's bugging me is the display. I'm outputting VGA, 1280x1024 @ 60 Hz, video clock being generated with a PLL at 108 MHz (and running the CPU module with 54 MHz - this 108 MHz divided by 2). Pixels are being output from a shift register clocked at 108 MHz.
Everything works fine except few random pixels appear at random places occasionally, and I can't figure out why with my limited knowledge. I'm guessing timing, but don't know why and how and where. Tried using timequest which reported a bad chain using a lpm_divide instance. I've modified it as pipelined and it improved from -100 to -16. However, this changed absolutely nothing. Fmax reportedly increased to ~66 MHz (which is still way below 108). What could be causing this? Metastability issues? Incorrect clock domain crossing?
I'm attaching a video to illustrate, fixed dots are supposed to be here, the flashing ones are not.
If you saw this in your own design, what would be your guesses about the cause and what steps would you suggest for me as troubleshooting? I'm out of ideas... :)
Thanks in advance for any suggestions or tips!
If you've got a ~40% miss in your Fmax, I'm amazed you're seeing anything close to what you are expecting. The short answer is that the signals you are expecting to be somewhere at a particular time.... aren't.
Can you post the failing timing paths and associated code?
What AndyN mentioned is valid, your fmax seems to not meeting the target requirement. You might need to look into the clearing the timing issue first.
By the way, what is the specific IPs that you are using to output the VGA signals? Are you using the Video IP Suite IPs?
Thanks for the feedback! I've caught the error in the meantime, it was a problem between my chair and keyboard :) Some row buffer was not getting emptied when it was filled with (too) many pixels. I've reversed the if condition so cleaning it comes first and problem went away. Apparently, it wasn't a timing issue.
The chain I was failing with a 40% in Fmax was unrelated with the vga, video or anything else I was using (it belongs to a HDMI part of code). I'll investigate why it fails so miserably, hoping to get HDMI working as well (didn't try yet, stuck to VGA for now).
I'm not using Video IP suite, just several lines of verilog to generate VGA signal (timing with few registers / counters). I plan to publish the source on GitHub, but it's so ugly right now I'm a little ashamed.
Unrelated question - Is it free to use altsyncram, altshift_taps and lpm_divide with Quartus Lite to build and distribute binary as well as sources?
Many thanks to all!