ENTITY Co IS
port (clk: in std_logic;
reset: in std_logic;
DCO: in std_logic;
Data_valid: out std_logic;
Data_in: in std_logic_vector(13 downto 0);
Data_out: out std_logic_vector (13 downto 0)
architecture Co_arch of Co is
signal count : std_logic_vector(13 downto 0);
if reset='1' then
elsif rising_edge(Clk) then
if DCO='1' then
I sent a sinusoidal signal through low frequency generator to ADC , but I didn't manage to get the same signal at the output of DAC,
I get an inversed signal, the question is how can I obtain the same signal, Did I miss something in the code ?
Is your DAC exepcecting signed or straight binary. Same for the ADC. What you are seeing is almost right and very common when there is a signed unsigned conflict. For example, if your ADC is returning a signed number, but your DAC expects straight binary, but you fail to offset it, you will see something like what you show.
Hi JEL W,
It looks like you missed a sign, either in code or in DAC or ADC settings, where you probably need to choose two's complement instead of offset binary which is chosen by default.