Help Needed: Implementing UART and SPI on Altera MAX II EPM240 CPLD

[Thiru_N]

Hi everyone,

I'm currently working with the Altera MAX II EPM240T100C5N CPLD and I'm trying to implement UART and SPI communication protocols on it. I'm using Verilog HDL and targeting a 3.3V logic level for interfacing.

Goals:

• Transmit and receive data using UART (preferably at 9600 baud).

• Interface with SPI peripherals (as SPI master).

• Trigger UART transmission (e.g., send byte 0xAA) every 100µs.

• Ideally get tested and working Verilog code examples for both protocols.

Questions:

1. Is the EPM240T100C5N suitable for implementing UART and SPI protocols purely in Verilog?

2. Are there any working code examples or recommended design practices for:

   • UART Tx and Rx

   • SPI Master

3. Can I reliably generate periodic signals (e.g., 100 µs interval) with the internal resources?

4. Any caveats or issues to watch out for when using these communication protocols on the MAX II CPLD?

My Setup:

• Device: Altera MAX II EPM240T100C5N

• Tools: Quartus II

• HDL: Verilog

• Clock: 50 MHz

• Power: 3.3V

• No onboard PLL

If anyone can share sample Verilog code or tips, that would be extremely helpful!

Thanks in advance!

— Thiru

[RichardTanSY_Altera]

It appears that you have posted two identical cases on the forum.

To ensure a more streamlined and efficient resolution process, we kindly request you to consolidate your inquiries into a single forum post.

We will continue the support in the other forum case (link below) and will transition this thread to community support.

https://community.intel.com/t5/Programmable-Devices/Help-Needed-Implementing-UART-and-SPI-on-Altera-MAX-II-EPM240/m-p/1707250#M100904

If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!

Regards,

Richard Tan