Help RAM

[Altera_Forum]

hi,  

i am quite new to vhdl and quartus ii. i have coded a 16x8 ram using vhdl in quartus , and y need a ram of 256kb , when y chage the address_width to 131072, that is the number of bits that y need, so when i try to compile appears this  warning (10639): vhdl warning at test.vhd(23): constant value overflow warning (10445): vhdl subtype or type declaration warning at test.vhd(23): subtype or type has null range warning (10034): output port "q[15]" at test.vhd(18) has no driver warning (10034): output port "q[14]" at test.vhd(18) has no driver . . . warning (10034): output port "q[0]" at test.vhd(18) has no driver  so ... how i make a ram of 256kb?  

[Altera_Forum]

256Kx8 is pretty large for inside an FPGA, but probably doable in some parts. The warnings have nothing to do with the size of RAM, but the VHDL, which nobody has. Double-click on the first message, and usually takes you to a location in the code(when possible) and start debugging that. The other messages may be an off-shoot from that initial error.

[Altera_Forum]

but... what is the correct way to do it? 

 this is my code ... but something is wrong in it ... help me  LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;  ENTITY Test IS  GENERIC  (  ADDRESS_WIDTH : integer := 131072;  DATA_WIDTH : integer := 16  );  PORT  (  clock : IN std_logic;  data : IN std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);  write_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);  read_address : IN std_logic_vector(ADDRESS_WIDTH - 1 DOWNTO 0);  we : IN std_logic;  q : OUT std_logic_vector(DATA_WIDTH - 1 DOWNTO 0)  ); END Test;  ARCHITECTURE rtl OF Test IS  TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0);   SIGNAL ram_block : RAM; BEGIN  PROCESS (clock)  BEGIN  IF (clock'event AND clock = '1') THEN  IF (we = '1') THEN  ram_block(to_integer(unsigned(write_address))) <= data;  END IF;   q <= ram_block(to_integer(unsigned(read_address)));  END IF;  END PROCESS; END rtl;

[Altera_Forum]

Hi Princess, 

 If you want 256 KB (assuming kilo-byte) of ram, that is 256 * 1024 = 262144 bytes  To store that many bytes, assuming that your memory is byte-addressable (location 1234 referts to 8 bits, location 1235 refers to the next 8 bits), you need to find the next greatest (or equal) power of 2. So:  2^0 = 1 2^1 = 2 2^2 = 4 2^3 = 8 ... 2^18 = 262144  So, ADDRESS_WIDTH is 18, not 131072. The ADDRESS_WIDTH parameter refers to how many wires represent your address (or, how many bits).  What's probably happening is that your synthesis/simulator tool can't handle a bus width of 131072 for a vector - this is incredibly large.  The other warnings are probably due to the same issue, as your synthesis/simulator tool appears to have assumed that the width of RAM is 0.

[Altera_Forum]

thanks, i understood it, but ... i think address_width have to be in bits, not in bytes ... so it would be 2 ^ 21 and put 21 in the address_width, andi get the following errors... please correct me if i'm wrong. 

 Error: Out of memory in module quartus_map.exe (2141 megabytes used) Error: Current module quartus_map ended unexpectedly

[Altera_Forum]

The calculation is clearly wrong. A 256 kByte RAM with a data with of 16 has 128 k words. This is equivalent to only 2^17 addresses, in other words an address width of 17 

 The reported Quartus out of memory error may result from trying to synthetisize an unavailable large RAM.  It may be meaningful to check first, if your present FPGA device has sufficient internal RAM. You would need at least an EP3C55 or larger Stratix device.

[Altera_Forum]

Also, are you sure you're smaller test case really uses the embedded memory? The out of memory error is not anything to do with memory in the FPGA, but that the physical RAM the synthesis process required was more than 2GB and the operating system probably capped it at 2GB. Under normal RAM inference, synthesis knows it's a single unit and it hardly uses any memory at all, but if the RAM gets synthesized into gates(registers, muxes, etc.) than it's an enormous structure(and surely not what you want).

[Altera_Forum]

Well, the original above design synthesizes as expected to an EP3C55 when using an address width of 17. However, Quartus apparently does nothing without utilizing considerable amounts of PC RAM. In this case it has to synthesize 215 LEs glue logic of multiplexers and decoders to connect the individual RAM blocks.

[Altera_Forum]

Didn't see DATA_WIDTH set to 16. My calculation was for the case where DATA_WIDTH set to 8, my bad. 

 Princess, the ram design inference that Rysc was referring to will be noted in the info or warning (I can't remember which one exactly) output during synthesis. Looking at the code, it looks like it should infer it, but maybe not.  I was going to suggest the following, but sync FvM already tried the design and it worked for him it probably won't have much fruit:  Also, it is going to generate a 2-port RAM since the address lines for read and write are different.   If you see nothing about ram inferrence in the synthesis log, you might want to try and see if it will synthesize as a 1-port module (use same address line for read/write), then if it works, it would appear as though quartus is having an issue with the 2-port implementation.

[Altera_Forum]

thanks a lot :)