Help!!!!! SDRAM interface Cyclone III.

Altera_Forum · ‎01-07-2012

I have a poject with SDRAM. I can create a interface with 128 MB SDRAM (BOTTOM or TOP). but, i don't know how to use full 256 MB SDRAM (BOTTOM and TOP). I use SOPC Builder to create system. Can you help me?

Altera_Forum · ‎01-08-2012

Is this a Cyclone III development kit? If yes, then tell the ALTMEMPHY that there are two memory chips by setting interface width to 32bits, 1 chip select and provide a proper address bus width.

Altera_Forum · ‎01-09-2012

ah! i wanna use 4 memeory chips (both 2 top and 2 bot). i can use 2 HPCs with 32bit interface each HPC, i compile design ok but when i run "hello world small" project that is "downloding ELF errors"? are there any wrongs in my system, please:

Altera_Forum · ‎01-09-2012

If it doesn't work then YES, something is wrong. But there could be many issues. Memory controller not working, wrong reset levels, bad memory chip connections, etc... Place On-Chip RAM in the design and start Nios from there. Upload memory checking software and run memory tests.

Altera_Forum · ‎01-11-2012

I don't know how to merge pll clock fanouts assigments when implementing multiple memory in SOPC builder. In "An 462" document writes "The force merging of pll clock fanouts assignment will automatically be assigned in the Quartus II software.", but how to check that they have merged.

I have another questions that is after generation in SOPC, in "An 462" document writes "add the sdc file and run the pin assignment tcl scripts", I don't know what name these files are?

Thanks!!!!!!!

Altera_Forum · ‎01-11-2012

You can add signal atribute to merge PLLs in assignment editor.

TCL scripts are located in project directory.

Altera_Forum · ‎01-11-2012

Tthanks a lot! I did it!

I added Ram onchip and check ok with "Hello world small". but the major problem is i can't still write or read into ddr2 sdram. i wonder i maped pins right?

module lab06 (

clkin_50,clkin_125, cpu_resetn,

ddr2bot_wen, ddr2bot_rasn, ddr2bot_casn,

ddr2bot_cke, ddr2bot_csn, ddr2bot_odt,

ddr2bot_a, ddr2bot_ba, ddr2bot_active,

ddr2top_wen, ddr2top_rasn, ddr2top_casn,

ddr2top_cke, ddr2top_csn, ddr2top_odt,

ddr2top_a, ddr2top_ba, ddr2top_active,

ddr2_dq, ddr2_dqs, ddr2_dm, ddr2_ck_p,

ddr2_ck_n);

output ddr2bot_active;

output ddr2top_active;

output [ 12: 0] ddr2bot_a;

output [ 1: 0] ddr2bot_ba;

output ddr2bot_casn;

output ddr2bot_cke;

output ddr2bot_csn;

output ddr2bot_odt;

output ddr2bot_rasn;

output ddr2bot_wen;

output [ 12: 0] ddr2top_a;

output [ 1: 0] ddr2top_ba;

output ddr2top_casn;

output ddr2top_cke;

output ddr2top_csn;

output ddr2top_odt;

output ddr2top_rasn;

output ddr2top_wen;

output [ 7: 0] ddr2_dm;

inout [ 63: 0] ddr2_dq;

inout [ 7: 0] ddr2_dqs;

inout [ 2: 0] ddr2_ck_n;

inout [ 2: 0] ddr2_ck_p;

input clkin_50;

input clkin_125;

input cpu_resetn;

nios_sys DUT (

// 1) global signals:

.clk_125 (clkin_125),

.clk_50 (clkin_50),

.ddr2_bot_aux_full_rate_clk_out (),

.ddr2_bot_aux_half_rate_clk_out (),

.ddr2_bot_phy_clk_out (),

.ddr2_top_aux_full_rate_clk_out (),

.ddr2_top_aux_half_rate_clk_out (),

.ddr2_top_phy_clk_out (),

.reset_n (cpu_resetn),

.sys_clk0 (),

// the_LED_pio

.out_port_from_the_LED ({ddr2top_active,ddr2bot_active}),

// the_ddr_bot

.global_reset_n_to_the_ddr2_bot (cpu_resetn),

.local_init_done_from_the_ddr2_bot (),

.local_refresh_ack_from_the_ddr2_bot (),

.local_wdata_req_from_the_ddr2_bot (),

.mem_addr_from_the_ddr2_bot (ddr2bot_a),

.mem_ba_from_the_ddr2_bot (ddr2bot_ba),

.mem_cas_n_from_the_ddr2_bot (ddr2bot_casn),

.mem_cke_from_the_ddr2_bot (ddr2bot_cke),

.mem_clk_n_to_and_from_the_ddr2_bot (ddr2_ck_n[0]),

.mem_clk_to_and_from_the_ddr2_bot (ddr2_ck_p[0]),

.mem_cs_n_from_the_ddr2_bot (ddr2bot_csn),

.mem_dm_from_the_ddr2_bot (ddr2_dm [7:4]),

.mem_dq_to_and_from_the_ddr2_bot (ddr2_dq [63:32]),

.mem_dqs_to_and_from_the_ddr2_bot (ddr2_dqs [7:4]),

.mem_odt_from_the_ddr2_bot (ddr2bot_odt),

.mem_ras_n_from_the_ddr2_bot (ddr2bot_rasn),

.mem_we_n_from_the_ddr2_bot (ddr2bot_wen),

.reset_phy_clk_n_from_the_ddr2_bot (),

// the_ddr_top

.global_reset_n_to_the_ddr2_top (cpu_resetn),

.local_init_done_from_the_ddr2_top (),

.local_refresh_ack_from_the_ddr2_top (),

.local_wdata_req_from_the_ddr2_top (),

.mem_addr_from_the_ddr2_top (ddr2top_a),

.mem_ba_from_the_ddr2_top (ddr2top_ba),

.mem_cas_n_from_the_ddr2_top (ddr2top_casn),

.mem_cke_from_the_ddr2_top (ddr2top_cke),

.mem_clk_n_to_and_from_the_ddr2_top (ddr2_ck_n[1]),

.mem_clk_to_and_from_the_ddr2_top (ddr2_ck_p[1]),

.mem_cs_n_from_the_ddr2_top (ddr2top_csn),

.mem_dm_from_the_ddr2_top (ddr2_dm [3:0]),

.mem_dq_to_and_from_the_ddr2_top (ddr2_dq [31:0]),

.mem_dqs_to_and_from_the_ddr2_top (ddr2_dqs [3:0]),

.mem_odt_from_the_ddr2_top (ddr2top_odt),

.mem_ras_n_from_the_ddr2_top (ddr2top_rasn),

.mem_we_n_from_the_ddr2_top (ddr2top_wen),

.reset_phy_clk_n_from_the_ddr2_top (),

// the_pll

.locked_from_the_pll (),

.phasedone_from_the_pll()

)

;

endmodule