Help !!!! Simulation Errors!!!!!!?!?!?!

Altera_Forum · ‎04-23-2008

Hello. I am trying to simulate my file, but I keep receiving error messages no matter what.

I am attempting to design a synchronous counter that outputs the the sequence 4-7-3-5-2.

I am completely new to CPLDs and VHDL....but I have to complete this project for school.

Here are the error messages I am getting:

Error: Simulation results from C:/altera/72sp2/quartus/Adam/syncount/db/syncount.sim.cvwf (0 ps to 100.0 us) do not match expected results from vector source file C:/altera/72sp2/quartus/Adam/syncount/syncount.vwf

Error: Logic level(s) do not match expected level(s)

Error: Logic level 100 does not match expected logic level XXX for node "q" at time 0 ps

Error: Logic level X does not match expected logic level U for node "state" at time 0 ps

Can someone help me out ?

Altera_Forum · ‎04-23-2008

More message please.

It may be the problem of the *.vwf file or your codes.

Altera_Forum · ‎04-23-2008

Ok. Well, I used an example in my text book to write vhdl for the counter. I used the example of code for a state machine. When I got up to the part of the process when you must "Start Simultation", I entered the end time and grid time for the .vwd file and entered the clock input and q outputs by using Node Finder. However, the example in my book shows that "State" was an assignment also, but the node finder shows state.s0, state.s1, and so forth, instead of showing just "State." I guess the tricky part started with the Node Finder. Ask me whatever you need to know, and I can tell you. Thanks for your time and concern.