Help about the connection between IC of voltage 5V and cyclone II

[Altera_Forum]

Now I've got a cyclone II(3.3v in doc) device.But I've only got a 5V D-A IC.Can I connect them directly?especially output from 5V IC input foot of cyclone II(3.3V in document).I know the signal output from cyclone II is able to detected by D-A IC successfully,But not sure if the signal from DA IC will damage the cyclone II....:confused:

[Altera_Forum]

--- Quote Start ---  But not sure if the signal from DA IC will damage the cyclone II  --- Quote End ---   Unfortunately, yes. I don't know, why you need a signal from DA converter to Cyclone II at all. Anyway, for a slow signal, a resistive divider is the most simple method. A 5 V tolerant logic gate suplied with 3.3V, e.g. 74LVC series can act as a level converter for fast signals.

[Altera_Forum]

--- Quote Start ---  Unfortunately, yes. I don't know, why you need a signal from DA converter to Cyclone II at all. Anyway, for a slow signal, a resistive divider is the most simple method. A 5 V tolerant logic gate suplied with 3.3V, e.g. 74LVC series can act as a level converter for fast signals.  --- Quote End ---   Thank you~~ Sorry....It's just a mistake(spell error)~~actually it's a ADC IC(TLC2543 --maybe an old device~~~but I've only got this in my lab).I can send the control signal to the IC,but not sure whether the data can transmit from IC to FPGA successfully.Ever I thought the method of using resistive divider too,but I'm afraid it will take additional unexpected puzzle.for 74LVC I'm not sure if the speed will be appropriate.I've just searched 74lvc157ADC to have a try.If it doesn't work,I think I'll buy a new A-D device........

[Altera_Forum]

--- Quote Start ---  for 74LVC I'm not sure if the speed will be appropriate  --- Quote End ---   Why? TLC2543 has maximum serial clock of 4 MHz.

[Altera_Forum]

--- Quote Start ---  Why? TLC2543 has maximum serial clock of 4 MHz.  --- Quote End ---   To tell the truth,I made my FPGA work at a clock of 50 MHz...I'm prefer higher speed~~~

[Altera_Forum]

Yes, no problem, but TLC2543 maximum interface speed is 4 MHz anyway. You have to use a clock divider for the IO clock.

[Altera_Forum]

Get a newer 3.3V IC its simpler and cheeper. You should take in consideration the FPGA price, if you do something wrong with your TLC2543 your FPGA will break.

[Altera_Forum]

Hi, 

I thought a serial resistor and turning the PCI clamping diode on in Quartus may worth thinking about. Searching for "Cyclone II 5V" resulted in an ALTERA desing hint  Problem   Can I turn PCI clamp diode on in Stratix®, Stratix II and Cyclone® II devices with external series resistor to make them 5V compatible? Solution   Yes, the input path is protected by PCI Clamp diode when you turn them on. Optional PCI clamp diodes are only available in column IO pins. Protection is achieved by clamping the pin voltage to VCCIO + 0.7V which is within the absolute maximum Vi. The VCCIO will be forced to 3.3V when PCI clamp diode is enabled. The solution given in Cyclone handbook which explains the implementation of PCI clamp diode with external resistor can be applied to all the other devices which are not 5.0V tolerant. The link to Cyclone handbook chapter 11 is stated below:  This might be a solution while perhaps going for a 3V3 ADC may at least be more future-proof solution ;)

[Altera_Forum]

In my opinion, PCI clamping diode are not safe in most applications, because they are not active between power up and FPGA configuration. Simple truth.

[Altera_Forum]

Hi, 

that was my thought, but ALTERA themselves provide this solution. I took a look in the referenced section in the Cyclone Handbook and they provide a calculation regarding this resistor as well.  Regarding the "missing diode" during configuration - yes the diode is not active during configuration and thus the pin may not be driven actively during configuration. As the input to the FPGA is the output of the ADC, I think this could be achieved by assuring the ADC is in reset condition until the FPGA releases the reset. Thus the output pin of the ADC should (if at all) just have a internal "weak" pull up connected to 5V - not driving actively during configuration.  Nevertheless - I would not implement this solution in a new design - I assume the 5V devices to get obsolescent during the next years (or rise in price to be unattractive...)  Carlhermann

[Altera_Forum]

--- Quote Start ---  ALTERA themselves provide this solution  --- Quote End ---   Right, but in my opinion it's a kind of misleading without mentioning the problem of unconfigured device behaviour. Of course, it works for those circuits, where can prevent the 5V device from driving out a high level in unconfigured FPGA state. For others (which are actually most circuits according to my experience), an external clamp diode or a different level conversion solution should be used. Anyway, I prefer the Altera way to those competitor devices that have permanent clamp diodes.

[Altera_Forum]

Hi, 

I agree with your thoughts and ALTERA in fact points to the problem of unconfigured state (by linking to the chapter of the device handbook). Maybe there were to many problems due to misuse (not observing the problem of unconfigured FPGA connected to 5V driven signals) as this design hint is only stated in Cyclone but not in CycloneII Handbook...  Carlhermann

[Altera_Forum]

--- Quote Start ---  use a clock divider for the IO clock.  --- Quote End ---    Ever I heard a problem about the clock divided by counter in FPGA is not steady enough .Though I've already given up this solution ,I still want to confirm whether I can use the clock divided by counter for devices directly .For this problem ,I have already seen various of opinions on the internet .

[Altera_Forum]

"not steady enough" is far from specifying a clear problem I fear. 

 Generally, didvided clocks can be used as peripheral clock. There may be problems: - to achieve a specific timing relation between the divided clock and the system clock when processing the pheripheral input or generating the output signals - the clock output can have glitches, if it's erroneously sourced by cominational logic rather than a register - jitter of the FPGA clock tree can be an issue in acquisition of high speed signals  Apart from the latter, the problems can be overcome. The best way to generate a peripheral clock with specified timing is using a PLL clock divider.