Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
19652 Discussions

Help needed in understanding "Net Delay Summary"

Honored Contributor II



Timequest Analyzer is reporting "Net Delay Summary" in red (Screenshot attached for the reference). Paths highlighted in red in the report are inside Qsys generated design. So, I do not have much control over the path. In general how important are these violations/report? 

The max delay (Required) shown in the analyzer is 2.00 for all the paths in the IPs inside the Qsys design. I do not understand how this can be same for all the paths?
0 Kudos
1 Reply
Honored Contributor II

All paths set to max delay can vary with a delay less than max figure. My understanding is that what matters at the end is the timing fail/pass with respect to setup/hold and max delay slack is only relevant if it is meant for some other purpose than timing e.g. metastability issues in dc fifos. If you have minor slack it may go away with build changes.