Help needed: large onchip memory on 3c120 board

[Altera_Forum]

Hi, 

 I am working on a video processing application on altera 3c120 board.   the video pipeline accesses ddr2_bottom memory. and thus t is isolated from niosII and other two SGDMA accesses.   The ddr2_top is accessed by   - one SGDMA for transfer of 640x480 (RGB) resolution video stream. (memory to stream)  - Nios II CPU for other processing.  I have set different arbitration values for these two masters for real-time video trasnfer.   There is one more SGDMA (stream to memory - minimum 320x240 grayscale ) needed to be used in this design.  I tried connecting this SGDMA master to the ddr2_top slave with various arbitration values. But somehow the program crashes after processing few frames.  to mention, the same program works fine with my older design, which had "1" arbitration value for all the masters connected to ddr2_top.   Is there any suggestion for using ddr2_top as the buffer for second SGDMA(stream-to-memory).. ?   --> I considered another option of using onchip ram as the buffer for second SGDMA(stream-to-memory), for which i need 75 Kbytes of onchip-ram. the compilation report without such a large onchip ram shows there are 50% memory bits used, which leaves roughly 228 Kbytes memory bits free for this board.   But when i instantiate 75 Kbytes onchip ram, it gives error saying this FPGA has 432 M9K blocks while, the design needs 441 M9K blocks.  I dont unserstand, where all the blocks are used. Is there any setting to use these free memory bits for onchip memory initialization ?   Any suggestions would be appreciated. Thanks in advance.

[Altera_Forum]

When you instantiate any core (i.e. NiosII with cache) which uses onchip memory as a buffer or fifo, it acquires onchip memory in single/multiple M9K based on design implementation.  

So lets take an example you need 1 kbits of onchip memory. Compiler will assign one full M9K block even if your usage is 1 kbits.  So memory usage you see on result may be less but how much M9K block it used is important. I hope this has clarified your doubt.

[Altera_Forum]

Thanks Ketan. 

 I realized that. Also, i forgot to remove the signaltap from design. afetr removing the signaltap, the design compiled successfully.  though, afetr recompilation, the design doenst work... :(  Can anyone please give some suggestions to solve the problem.