Help on creating interface between nios processro system with verilog logic

[Altera_Forum]

Hi all, 

I am using nios processor system with some pheripherals and a verilog logic(I got that verilog code from opencores ) in my design.My goal is to send signals (data) from my nios processor to verilog logic and receive the data to nios processor from verilog code. I have a clock_out port from my verilog logic, I have to use that as clk for my nios processor.I have to use some of the ports of verilog code as signals from my nios processor some ports just stay like ports (those are just few leds).Is there someone can give me some Idea,How it can be implimented.The bad thing is, I am new to both Nios and verilog (I am VHDL guy :)).and one more thing, I am using DE0 nano board and it has no enough input ports.ofcourse I can use external addon board,but I want to use system console send and receive signals from my nios processor.I have gone through some documents but got very little details.I appreciate your help,If some one post some links,where I can get some better documents with some examples. Thanks in advance, Sarat

[Altera_Forum]

For slow signals such as leds or buttons you can just use a PIO component in the SOPC builder project, this will create input or output ports that you can control from the software. 

If you need faster data transfer then you'll probably need to design a custom SOPC component. One way to do this is to format your data as an Avalon Stream and use a SGDMA to read/write the data from the main memory to/from your component. If you need to change of clock domains between the CPU and your logic, you can use a dual clock avalon stream fifo in the SOPC builder project.

[Altera_Forum]

Hi, 

Thank you for reply.As you said I have already had 2 PIOs in my sopc builder. One PIO (bidirectional ) for sending and receiving data and one pio for controlling.But the thing is I have two different designs now One is nios system and other is verilog logic. I want to combine these two systems for my final design.Can you please tell me how to do that (combining nios system and user logic ). sarat

[Altera_Forum]

The SOPC subsystem in a component that you can instantiate in your own code. I don't do verilog, but it should be about the same than with vhdl. Look in the generated files if you have a *_inst.v file, it should contain what you need to instantiate the SOPC component in your own verilog file.

[Altera_Forum]

Hi, 

You are right. I forgot that beauty,component:). I will use my nios system as component. Thank you very much for your help. Sarat