Help using verilog files in Quartus

[Altera_Forum]

Hi, 

I’m a beginner using FPGAs and also programming in Verilog or VHDL. I have two Verilog files created in the same Quartus 9.0 project, lets say file A and file B. File B finishes a process that file A started. How can I put in file A that I need file B to continue, without copying all the code from file B to A?. Like using a black box, just declaring file B in A.   Thank you.

[Altera_Forum]

It should be possible to use the `include command. `include the file you want to use and then compile only the top file. 

 -Vinay

[Altera_Forum]

Depending on what you are doing, you may not need to do this at all. If for instance all you are doing is referencing other modules, the tool (Quartus) will automatically find the other module assuming you've set up your project paths and files appropriately. 

 A "`include" directive is like copying and pasting the code from the other file into the present file.  Jake