Help with Altera Cyclone III AS configuration problems.

[Altera_Forum]

Hi, 

  I've tried to make a development board for the Cyclone III, most of it works as far as I can tell without the FPGA.   My problem is with the FPGA configuring after I have successfully downloaded the configuration file to the serial memory. Referencing this document:   https://www.altera.com/en_us/pdfs/literature/hb/cfg/cfg_cf51001.pdf   I can tell what stage the FPGA is in when powering up. Well nothing happens. The FPGA just sits there with NCONFIG at 0V, CONFIG_DONE at 0V and NSTATUS at 0V.   I have gone over the pins and connection scheme and unfortunately haven't found any problems!   Attached is my schematic, it has some errors but I have made a rev1.1 schematic and changed those. One of those is the schematic says I'm using 1MB of memory when I'm using 16MB. I show rev1.0 as this is the revision of the board I'm working on.   Thanks for any help!

[Altera_Forum]

Or can someone provide me a schematic of AS implementation that is proven to work so I can compare? 

 Thanks

[Altera_Forum]

Anyone? 

 Thanks

[Altera_Forum]

I'm seeing a couple of things: 

 JTAG is not used, and not disabled. This can cause the device to get into a funk.  TMS, TDI should be pulled to VCCA, TCK should be pulled to ground.  MSEL's should be tied to either VCCA (2.5V) or GND. You have it hooked up to 3.3V  More General debugging:  All all the power supplies up and at their nominal values?   Is The Active serial clock,Data and Chip select toggling at all?  If you can hook up a JTAG header, can you get a device id out of the part through JTAG?  Pete

[Altera_Forum]

Most likely is the JTAG pins left floating which stop the device from working, as Pete has mentioned. Also make sure the bottom metal pad on the FPGA package is grounded. Please check that each and every FPGA pin follow the rules listed in this document: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone3/pgc-01003.pdf

[Altera_Forum]

Since you mentioned the nCONFIG and nSTATUS is 0V when powering up, then you may need to check the power circuitry on the board. If FPGA is not power according to the POR spec, then nCONFIG will not be release.