Help with Signal Tap II

[Altera_Forum]

Hi, i am running some tests with a designe, but as it is a prototype there are a few jump wires between two boards. I am trying to take a look at a signal with logic tap II and USB Blaster on a Cyclone II. I am looking at 2 input pins with no pull-up or pull-down. I have a small problem, the trigger seems to be too sensitive.. and if i leave it open or power-up the other board, it trigger randomly. I am looking at the signal right near the FPGA with a 100Mhz Scope.. but the scope does no trigger.... Any idea why the signal tap is so sensible? What i am looking is just some random signal, or is the real signal that is driving the FPGA logic? 

 Thank you!

[Altera_Forum]

You may also trigger the inputs on touch. They are apparently floating until they are driven by external source. You can use weak pullup as a remedy.

[Altera_Forum]

But does that really trigger my logic? One of the signals is a clock control signal driven by a mcu. The problem is that both will be further powered.. and i am afraid a random pulse is generated...

[Altera_Forum]

--- Quote Start ---  Hi, i am running some tests with a designe, but as it is a prototype there are a few jump wires between two boards. I am trying to take a look at a signal with logic tap II and USB Blaster on a Cyclone II. I am looking at 2 input pins with no pull-up or pull-down. I have a small problem, the trigger seems to be too sensitive.. and if i leave it open or power-up the other board, it trigger randomly. I am looking at the signal right near the FPGA with a 100Mhz Scope.. but the scope does no trigger.... Any idea why the signal tap is so sensible? What i am looking is just some random signal, or is the real signal that is driving the FPGA logic?   --- Quote End ---    The input buffers on the FPGA I/O pins are like very high gain amplifiers. Given that you have no pull-up or down on the FPGA pin, the output of the input buffer will toggle high or low, and will trigger SignalTap; keep in mind that SignalTap is probing the output of the buffer, not the pin of the FPGA.  The scope will only see the wiggles on the signal on the input pin, it does not see the effect of the FPGA buffer, so you will not see the same thing as SignalTap.  If you route the input signal to an output pin, then probe that output pin with your scope, then you will see a similar signal to SignalTap.  Cheers, Dave

[Altera_Forum]

Ok thank you for the explanation. I managed to solve the problem with a weak pullup on a enable pin, so if the enable pin goes to 0, for sure the microcontroller will be operational so i wont have any floating pin.  

 Thank you!