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mark_lee
New Contributor I
106 Views

Helpless about "GE 1588 V2 1PPS SYNC "

Hi  team

     I had  debug  GE 1588 V2  in my board is Slave ,  and Third party equipment is Master。The 1PPS  signal output  from my board is sync to the 1PPS signal output from the Master equipment, but threre are  something  wrong,  the slave 1PPS Falling edge  sync to the Rising edge of the master equipment 1PPS.

    How  can i make the Rising edge sync to Rising edge  between the slave and the master

屏幕截图 2021-04-21 193703.png

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6 Replies
mark_lee
New Contributor I
75 Views

hello  anybody

mark_lee
New Contributor I
74 Views

Did I put the post in the wrong board?

Deshi_Intel
Moderator
59 Views

Hi Mark,


I am afraid we won't be able to provide assistance to you on the offset adjustment.


This is due to Intel FPGA IP does not implement event messaging protocol layer, but only provide basic hardware capability (i.e. timestamping) in implementing 1588 protocol


User logic will manage PTP messaging and corresponding offset adjustments. My understanding is the offset algorithm is typically managed by high level software stack.


Another suggestion to you is perhaps you can check back with your test equipment vendor to see if they are able to provide you further guidance or any setting that can fine tune in the test equipment or not.


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
58 Views

Another suggestion is you can also try play around with the sync mode of the "TOD sync IP" page 13, table 14


mark_lee
New Contributor I
47 Views

Hi Deshi 

         Thanks for your guidance , I will try to play around with the sync mode and test with another test equipment.

Deshi_Intel
Moderator
43 Views

HI Mark,


Sorry, pls ignore my suggestion on the TOD sync IP - sync mode setting.


I clarified further with Intel internal team.

  • The TOD sync IP is just good to sync up the master TOD and slave TOD IP within the FPGA internally.
  • It won't help to sync the offset between PTP slave device (FPGA) and PTP master device (your test equipment)


Ultimately user is still expected to build your own design algorithm to adjust the PTP offset btw master and slave device yourself. From Intel FPGA Ethernet IP side, we only provide the timestamp info but not the offset adjustment solution


I dig through some reference design and found below example design that comes with PTP offset adjustment software stack solution.


Thanks.


Regards,

dlim



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