High Level, Low Level, stratix II.

[Altera_Forum]

I have a data signal with low voltage peak to peak (only 0.5 volts). I want my stratix II FPGA to understand it as a zero and one.  

 To do that I tried changing my input from 3.3v to 1.5, but quartus II gave me an error saying this input pin is stuck at 3.3. Does that mean I can never change it to 1.5?  In addition, this pin, or these group on input pins are the only general IO available on my board, which is the transceiver SI development board. I have no other options but to use them.  To solve that problem, I tried to add DC shifting to my input, around 2volts. Yes, this kind of solved the problem but its unstable. Like 2volts will give totally different results than 1.99volts or 2.01 volts.  Any suggestions? (I dont wanna amplify or play with the original signal).

[Altera_Forum]

Use comparator. set your ref voltage to 0.5v and connect comparator power to 

3.3v. your output will be 0 or 3.3v if less then 0.5 will be 0 if more then 0.5 will be 3.3v  Andre

[Altera_Forum]

you can also try using differential signaling, with one side stuck at 0.5V and the other one being your signal

[Altera_Forum]

Yes, Stratix II LVDS common mode range is said in the datasheet to start from 200 mV.