High fan-out signal

[Altera_Forum]

Hello; 

After compiling my design in qurtusII, I found this signal "clk~inputclkctrl" have a high fan out. the node"clk" is the clk signal in my design. what can I do to solve this problem. Thanks.

[Altera_Forum]

--- Quote Start ---  this signal "clk~inputclkctrl" have a high fan out (...) what can I do to solve this problem  --- Quote End ---    Is this a problem at all ? As far as I know, clocks need to have the ability to drive signal for a large amount of devices.

[Altera_Forum]

Quartus knows about high fanout for clocks and will insert additional logic as needed to compensate for it. You don't need to do anything in most cases.

[Altera_Forum]

I see you have already found this (http://www.alteraforum.com/forum/showthread.php?t=52117) other thead, but for others who come across this thread: you might get some info there.