Hold time violation from PLL

[Altera_Forum]

Hi ,  

  My input clock is 50 Mhz and i am using PLL to generate 6 Mhz (Stratix III) . But i am getting violation e.g   0.854 core_m28:CORE_INST|mem_bank:mem_bank_INST|ev_fifo_rd_data_d[6] core_m28:CORE_INST|ICN1:Interconnect_system_INST|GenericConv_5_c6sb0_genconv_top:GenericConv_5|GenericConv_5_c6sb0_tconv_3to1:c6sb0_tconv_3to1_0|t3_r_data_reg[1][6] FPGA_PLL_INST|altpll_component|auto_generated|pll1|clk[0] FPGA_PLL_INST|altpll_component|auto_generated|pll1|clk[0] 0.000 2.659 1.865   How can i resolve this violation ?    currently constaint is specified like this  create_generated_clock -name {FPGA_PLL_INST|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {FPGA_PLL_INST|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 3 -divide_by 25 -master_clock {i_osci_clk} [get_pins {FPGA_PLL_INST|altpll_component|auto_generated|pll1|clk[0]}]

[Altera_Forum]

Are you sure you are not gating the 6MHz clock?

[Altera_Forum]

i am gettign 6 Mhz clock , but there are some violations on the ARM core , i am using ARM core (core_m28, Vhdl code ) in my desing and 6 Mhz clock goes to the ARM core , where i see the violation .  

e.g  0.854 core_m28:CORE_INST|mem_bank:mem_bank_INST|ev_fifo_ rd_data_d[6] core_m28:CORE_INST|ICN1:Interconnect_system_INST|G enericConv_5_c6sb0_genconv_top:GenericConv_5|Gener icConv_5_c6sb0_tconv_3to1:c6sb0_tconv_3to1_0|t3_r_ data_reg[1][6] FPGA_PLL_INST|altpll_component|auto_generated|pll1 |clk[0] FPGA_PLL_INST|altpll_component|auto_generated|pll1 |clk[0] 0.000 2.659 1.865