Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Hot FPGA!

Altera_Forum
Honored Contributor II
3,243 Views

My FPGA gets really hot after configuration. I've checked my power pins, and they are all connected to the correct supplies which are all within tolerance. Any other suggestions?

0 Kudos
13 Replies
Altera_Forum
Honored Contributor II
1,197 Views

A common mistake I've seen is related to the Quartus Unused I/O setting which, by default, is set to 'Outputs Driving GND' and those I/O are connected (directly) to VCC on the board. Make sure that this is not the case - as this will not only increase current consumption, but also damage the I/O buffer.

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

Another possibility is that you have a metastability problem caused by asynchronous logic. I have seen devices heat up real fast if you are not using synchronous design practice.

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

You may have forgotten to pull up the TCK pin. It's really sensitive and will pick up RF noise really quickly.

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

Yeah, you're lucky if your unused pins are set to "Output, Driving Ground" and all that happens is that your chip gets hot. I've seen some designs where that destroys components. In general, I think it's safer to stick with "As Inputs, Tri-stated". 

 

Cheers, 

 

-uraslacker
0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

Bee Gee, 

Which FPGA are you using? You can also check the current reported by the early power estimator (EPE) versus the current you measure on your board.
0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

I would check the supply voltage of your PLL's...

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

I concur with Karl. VCC for PLLs should be Vcore level, not VCCIO...

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

Yes. Follow the Operating Conditions section of the datasheet or handbook and the pin table information and that will cover the PLL VCC connections.

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

 

--- Quote Start ---  

A common mistake I've seen is related to the Quartus Unused I/O setting which, by default, is set to 'Outputs Driving GND' and those I/O are connected (directly) to VCC on the board. Make sure that this is not the case - as this will not only increase current consumption, but also damage the I/O buffer. 

--- Quote End ---  

 

:D Thanks! 

I had the same problem and just figured out what was wrong!
0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

 

--- Quote Start ---  

Yeah, you're lucky if your unused pins are set to "Output, Driving Ground" and all that happens is that your chip gets hot. I've seen some designs where that destroys components. In general, I think it's safer to stick with "As Inputs, Tri-stated". 

 

Cheers, 

 

-uraslacker 

--- Quote End ---  

 

 

 

"As input tri-stated" can result in high current and device overheating if a dedicated input or I/O pin is completely floating on the board. The input buffer could oscillate. Refer to the .pin file produced by the Fitter to see how to connect each pin. The .pin file will tell you to connect pins that are not supposed to be left floating. 

 

If your particular device allows it, it would be safer to set "Device and Pin Options --> Unused Pins --> Reserve all unused pins" to "As input tri-stated with bus-hold circuitry" or "As input tri-stated with weak pull-up resistor". 

 

If you know you have a particular spare pin grounded on the board, the weak pull-up would of course use a little power. (Bus hold on a grounded pin is fine.) For specific pins you have grounded on the board, use the Assignment Editor to set "Reserve Pin" to "As output driving ground". You can use "Reserve all unused pins" for the rest of the spare pins instead of an Assignment Editor setting for each one.
0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

Good suggestions from all. I'd like to add, if you have a way of measuring power supplied to the core or bank power supplies, check to see which is responsible for supplying all the current. If it’s the core, then it’s not I/O contention problem (i.e. IO set as GND driving against VCC on the board). If you can turn off clocks, then it could be asynchronous circuit free running as someone indicted. If it’s the I/O, along with the suggestions already provided in previous posts, check buses to make sure no two chips are contending also.

0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

 

--- Quote Start ---  

:D Thanks! 

I had the same problem and just figured out what was wrong! 

--- Quote End ---  

 

 

What was the actual problem.? 

 

My fpga board is heated up now and I am scared if the board is spoilt. My program was running which i could visualize by the blinking LEDs. So it means that the Fpga is not spoilt right?
0 Kudos
Altera_Forum
Honored Contributor II
1,197 Views

What was the actual problem.? 

 

My fpga board is heated up now and I am scared if the board is spoilt. My program was running which i could visualize by the blinking LEDs. So it means that the Fpga is not spoilt right?
0 Kudos
Reply