In An 692 says: "Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 devices do not support 'Hot-Socketing' except under the conditions stated in the tablebelow. The tables below also show what the unpowered pins can tolerate during power-up and power-down sequences.". And given a table which shows the modes power-up and power-down. I do not understand, does the transceiver GX support Hot-Socketing mode or not? Сan I remove or insert spf+ modules direct connected to transceivers in power-on mode?
Hi,Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 device LVDS I/O pins do not support ‘Hot-Socketing; Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 device transceiver pins do not support ‘Hot-Socketing which indirectly implies to SPF. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Hi,Why the Arria 10 transceiver pins and sfp+(and qsfp) are connected directly on the Arria® 10 GX FPGA Development Kit? https://alteraforum.com/forum/attachment.php?attachmentid=15185&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15186&stc=1
This is a pertinent thread and I also have some questions:1) How do we know that Transceiver Rx signal levels are <1.1 Vp-p? Can we infer that they will be safe if connected to other Altera Transceiver Tx outputs or must they be actually measured at the device balls? 2) What does it mean to drive to VCCIO if powered down? Does this mean the local VCCIO (which will also be powered down by definition) or the remote active VCCIO? 3) What do the '-' cases mean? Do these mean that these cases are not allowed or can't happen???