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How can I connect an IO-PLL output clock to a reference clock input of a transceiver?

I have a ref clock of 312.5 MHz as input at the FPGA, a transceiver which requires 322.265625 MHz and 5.15625 GHz as reference clock inputs. The 5.15625 GHz can I make with a fPLL or ATX-PLL and connect to the transceiver. The 322.265625 MHz can I make with an IO-PLL, but the fitter complains when connecting the output of the IO-PLL to the transceiver. It is the rx_cdr_ref_clk_10g input pin of the transceiver.

 

Is there a workaround for this? I am using the transceiver for a 10 Gbps optical link and as far as I know the 322.265625 MHz is required.

 

Best regards

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Which IP and device part number you are using ? So I can try it out and create one example design and send to you.

 

 

Thank you ,

 

Regards,

Sree

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Beginner
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Dear Sree,

 

I am using the Arria 10 (10AS027E4F29E3SG) as device part and the IP I am using is the "1G/10GbE and 10GBASE-KR PHY Intel Arria 10" (where the 1 GbE interface is disabled). I want to use it in combination with the "Low Latency Ethernet 10G MAC". I also use the "Transceiver PHY Reset Controller".

 

Best regards,

 

Frank

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Hello Frank ,

Thank you for the input ,

I could able to do fitter compliation passed with two method as below

i) IOPLL output connected to FPLL aand FPLL generate the required datarate clock. (More jitter )

ii) FPLL output connected to ATX PLL and ATX PLL generate the required datarate clock. (Recommeded Method)

 

Here is attached example design for your reference and let me know if you have any question/concern

 

Note : This is not complete design for 10G KR base PHY ; just to make sure i can route the XCVR PLL use Fabric PLL.

 

Hope Helps

 

Thank you ,

 

Regards,

Sree

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Beginner
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Dear Sree, First of all, thank you for your support. However, I am not able to open the archived project file. I tried it with Quartus 19.2 Pro, could that be the problem (according to the filename it looks like you used 19.3)? The corresponding logging: ******* Archived project restoration attempt on Tue Jan 21 13:48:30 2020 Source archive file: /home/frank/proj/pit17018/tmp/intel support/a10_xcvr_fpll_19_3_0_222.qar Quartus Prime failed to read the archive or extract some files into /home/frank/proj/pit17018/tmp/intel support/a10_xcvr_fpll_19_3_0_222_restored/. ======= Files failed to restore before extraction terminated: ====== Met vriendelijke groeten / With kind regards, *Frank van Eijkelenburg* Lead Designer *T* +31(0)182594000 | *E* frank.van.eijkelenburg@technolution.nl <http://www.google.com/url?q=http%3A%2F%2Flinkedin.nl%2F%253C%253Cvoornaamachternaam%253E%253E&sa=D&s...> *A* Burgemeester Jamessingel 1, P.O. Box 2013, 2800 BD Gouda, The Netherlands | *W* technolution.com This e-mail is intended exclusively for the addressee(s), and may not be passed on to, or made available for use by any person other than the addressee(s). Technolution B.V. rules out any and every liability resulting from any electronic transmission.
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Hello Frank ,

Sorry i didnt check with you the quartus version to be use before I start and yes I used 19.3 pro version.

If iam not mistaken , i dont think so we have backward compatibilityoptions in quartus.

Anyway i will change the design to 19.2 pro and attach it

 

Thank you ,

 

Regards,

Sree

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Hello Frank ,

Attached 19.2 pro design for your reference.

 

Thank you ,

 

Regards,

Sree

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Beginner
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Dear Sree,

 

Thanks again. I was able to build your design. I will try to connect it at the same way in my own design.

 

Best regards,

 

Frank

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