How can I fix a Quartus FITTER problem when there is no error reference from database? (Pins assignments and ALTLVDS_TX)

[CFDia]

Hello Folks,

I have a Quartus custom (no-OS) project for a Stratix IV board which works with an AD9361 daugther board. The project synthesize perfectly and I able to use AD9631 as it should be.

Now, I need to port the project to Stratix V and, of course, pinout is different. I started the project from zero adding step by step all the required Megafunctions. One specific function is the ALTLVDS_TX which I use for AD9631 transmit interface and I presume that could be the source of the problem.

The "Analysis and Synthesis" step finish without error. On the other hand, Fitter presents the following error:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS clock tree(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (175001): The Fitter cannot place 1 LVDS clock tree.

Info (14596): Information about the failing component(s):

Info (175028): The LVDS clock tree name(s): ad9361_itf:ad9361_itf_inst|lvds_adapt_tx:lvds_adapt_tx_inst|tx_lvds_ip:tx_lvds_ip_inst|altlvds_tx:ALTLVDS_TX_component|tx_lvds_ip_lvds_tx:auto_generated|pll_fclk~PLL_LVDS_OUTPUT~quadrant

Error (16234): No legal location could be found out of 4 considered location(s). Reasons why each location could not be used are summarized below:

Error (175006): Could not find path between the LVDS clock tree and destination pin

Info (175027): Destination: pin hsma_tx_d_p[5]

Info (175015): The I/O pad hsma_tx_d_p[5] is constrained to the location PIN_AD9 due to: User Location Constraints (PIN_AD9)

Info (14709): The constrained I/O pad is contained within this pin

Error (175022): The LVDS clock tree could not be placed in any location to satisfy its connectivity requirements

Info (175021): The pin was placed in location pin containing PIN_AD9

Info (175029): 3 locations affected

Info (175029): LVDS_CLK_TREE_X1_Y0_N1

Info (175029): LVDS_CLK_TREE_X1_Y107_N1

Info (175029): LVDS_CLK_TREE_X81_Y107_N160

Error (175006): Could not find path between the LVDS clock tree and destination pin

Info (175027): Destination: pin hsma_clk_out_p2

Info (175015): The I/O pad hsma_clk_out_p2 is constrained to the location PIN_G9 due to: User Location Constraints (PIN_G9)

Info (14709): The constrained I/O pad is contained within this pin

Error (175022): The LVDS clock tree could not be placed in any location to satisfy its connectivity requirements

Info (175021): The pin was placed in location pin containing PIN_G9

Info (175029): 1 location affected

Info (175029): LVDS_CLK_TREE_X81_Y0_N160

I read several posts with related information but, unfortunately, I continued clueless. Can someone explain to me what is going on and how I could possibly solve this?

This porting supposed to be only a pin exchange, shouldn't it?

Please, request more information whenever is necessary.

UPDATE:

After several iterations, the following pin assignments gives the error message:

set_location_assignment PIN_AD9 -to hsma_tx_d_p[5]

set_location_assignment PIN_AE9 -to "hsma_tx_d_p[5](n)"

set_location_assignment PIN_AB12 -to hsma_tx_d_p[7]

set_location_assignment PIN_AC12 -to "hsma_tx_d_p[7](n)"

set_location_assignment PIN_K9 -to hsma_tx_d_p[11]

set_location_assignment PIN_J9 -to "hsma_tx_d_p[11](n)"

set_location_assignment PIN_AB9 -to hsma_tx_d_p[6]

set_location_assignment PIN_AC9 -to "hsma_tx_d_p[6](n)"

Why does it work for other pins and not for the ones listed above? Are they reserved for something? Can someone shed light on this, please?

[Rahul_S_Intel1]

Hi ,

Can you please share a sample project for debugging.

[CFDia]

Hi,

I'm sorry for the delay. I have prepared a sample of my project that is having the issue. Please, take a look in the attached file.

After synthesis, you will get the same errors decribed above. I used Quartus II V18.0.

BR,

CFD