I have been trying to create a simple Avalon-MM Master to read from a PIO slave (push buttons), however I am reading only 0's on the readdata line.
wire [31:0] master_0_master_address; wire master_0_master_read; wire [31:0] master_0_master_readdata; reg [1:0]currentState; reg [1:0]nextState; reg [31:0] data; reg [31:0] address; reg read; assign master_0_master_address = address; assign master_0_master_read = read; assign led11[3:0] = ((reset_reset_n == 0)) ? 4'b1111 : (data[3:0]); always @ (*) begin if(~reset_reset_n) begin data <= 32'b0; nextState <= 2'b0; end else begin case (currentState) 2'b0: begin address <= 32'b100000; read <= 1; if(master_0_master_waitrequest) nextState <= 2'b10; else nextState <= 2'b1; end 2'b1: begin read <= 0; data <= master_0_master_readdata; nextState <= 2'b0; end 2'b10: begin if(master_0_master_waitrequest) nextState <= 2'b10; else nextState <= 2'b1; end endcase end end always @ (posedge clk_clk or negedge reset_reset_n) begin if(~reset_reset_n) currentState <= 0; else currentState <= nextState; end
And the Qsys system:
I'm guessing that the signal names preceded by "master_" are your interface signals because I don't see a port list for your component. Is that correct?
Have you tried just leaving read enabled all the time and just do reads on waitrequest going low?
Yes, the signals preceded by "master_" are my interface signals. I have somehow managed to get it working. However, I have noticed some weird behavior: No matter the address I place on the master_0_address line, the state machine reads the pushbuttons' data register just fine. But if I add another PIO slave (LEDs) to the project, assign addresses, and then generate the files, then my code does not work anymore - I get 0's again. Seems like the issue is with slave addressing.
When I add the second PIO slave, Qsys assigns 0x0000_0000 to the pushbuttons, and 0x0000_0010 to the LEDs. To read from the pushbuttons' data register, I do master_0_address <= 32'b0. I am not sure if I need to add an offset to the address shown in Qsys or.. According to this document, the data register comes first, so there is a 0 offset to the address shown in Qsys.
Thanks for your help.