- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello everyone,
I am trying to make IIR filter, which is attached to this thread in pdf, with cyclone III. Since there are some multipliers in floating point, I use FLoating Point Megafunctions especially alftfp_add_sub and altfp_mult. Here is my problem: because altfp_add_sub cannot deal with input with 'U', the first alftfp_add_sub (named as altfp_add_sub0 in the pdf) can only output 'U' and therefore all inputs to other blocks are always 'U'. So what I am trying to do to solve this problem is to give initial condition(s) to the blocks especially the first altfp_add_sub so that the output will be normal value. Does anyone know how to set initial condition to Floating Point Megafunctions?? If there is no way, then I want to know other ways to solve this problem... I appreciate any help. YukihiroLink Copied
4 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
It might be that aserting aclr (not connected in your design) changes the behavior. My reading of the Floating-Point Megafunctions users guide however is, that the IP isn't prepared to produce defined output during startup. In this case, you may want to add a multiplexer to the design that feeds zero to the IIR loop for some clock cycles to reset the filter.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear DvM
Thank you for your reply. --- Quote Start --- My reading of the Floating-Point Megafunctions users guide however is, that the IP isn't prepared to produce defined output during startup. --- Quote End --- I also read the users guide and got the same answer as you mentioned. It's pretty weird that signal initialization cannot be done. Anyway --- Quote Start --- In this case, you may want to add a multiplexer to the design that feeds zero to the IIR loop for some clock cycles to reset the filter. --- Quote End --- I tried to realize this but got new problem. Multiplexer needs "switch" signal to choose which input signal is to be read out. Since undefined signals can not be read as "undefined," I think it's impossible to produce the switch signal nor asynchronous clear signal. Hence I cannot reset my filter... Please help me out...- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Since undefined signals can not be read as "undefined," I think it's impossible to produce the switch signal nor asynchronous clear signal. --- Quote End --- I can't follow your reasoning. A mux can insert a value of zero into the loop during initialization. The design must be already clocked.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear FvM
Thanks for your reply. As far as I knew, undefined signals ('U's) could not be detected since they are "undefined." But I just tried to detect them using "if" statements (like
if not(dataa(i) = '1') and not(dataa(i) = '0') then
--blahblahblah
) in my VHDL, I noticed I could detect them. Sorry for my poor understanding... Anyway, using the logic above, I could deal with my problem. Thanks alot, Fvm

Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page