I'm working with a design that involves a 10CX220YU484E5G receiving data from four devices over LVDS interfaces. All four devices that we're receiving data from are the same part, and one crystal provides the clock to all of them. From each device, we're receiving the following 6 signals over the LVDS interface (see attached):
• Four “data” lanes
• One “valid” signal that is high when the “data” lanes are valid
• One DDR bit clock
The DDR bit clock frequency is 300 MHz, so the throughput is 600 Mbps per data lane. Two of these devices are routed to bank 2A and two of them are routed to bank 2J. Unfortunately, this means two devices have to share the I/O PLLs in bank 2A and 2J; we just don't have enough I/O PLLs for each device to have its own. In each bank, one device's "clock" is connected to the I/O PLL's dedicated clock input. As all four devices have the same crystal as their clock source, the frequency of their bit clocks are exactly the same with some random phase difference from device to device. Our plan was to use a 10-channel LVDS receiver with DPA, with the hope that the DPA could correct for that phase difference. However, when I look at the captured data, I can tell that the word alignment for the 2nd device in each bank isn’t working properly. Note that the data doesn’t include sync words or a training pattern; the only way for us to do word alignment is to use the rising edge of the “valid” signal. It makes sense that the DPA is struggling with this, as the valid signal has very few edges for the DPA to work with.
My question: is it possible for us to "look into" the LVDS SERDES IP to see which DPA phase each channel has locked to? As a workaround, I'd like to use the DPA to lock to the bitclock from each device and then provide the DPA phase which is shifted 90 degrees ahead of that to the receiver to sample the "data" and "valid".
Hi Eng Wei,
Thanks for your response. I could probably modify the design to strip out everything except for the receivers, but my request really boils down to the question: how do I determine which I/O PLL phase a DPA receiver has locked to?
The DPA of the receiver will select the clock with correct phase automatically and it is depends on the configuration of the receiver IP that we have selected.
We shall validate the output of the receiver if correct output bits are received.
Hi Eng Wei,
I have reviewed the relevant sections of the Core Fabric handbook, but they don't answer my question. Let me rephrase it. Suppose that the DPA for one channel has locked to a specific I/O PLL phase, say, 45°. I can tell that the channel is locked because rx_dpa_locked is asserted for that channel. However, how can I check which phase (in this case, the 45° phase) that channel has locked to? I am hoping to use this information to explicitly select an I/O PLL phase to sample related channels. These related channels have very few data transitions, so we can't use the DPA for them. But, they have the same clock-to-data phase relationship as the channels that we can use DPA for.
We can refer to Section "Initializing the LVDS SERDES IP Core in DPA Mode" in the doc below:
In steps number 4:
Apply the DPA training pattern and allow the DPA circuit to lock.
We can refer to datasheet below, taking Arria 10 device as example, to check for DPA lock time specs which can be applied to each channel after rx_dpa_reset port is deasserted:
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