Our team wants to implement an FPGA system that controls DAC Resolution 1ns width.
The FPGA now in use is using Cyclone V (5ceba2f23c7). The 40MHz crystal clock is received from the outside, multiplied by 150 MHz with the Quartus PLL, the DATA and DAC CLK are synchronized to the DAC chip.
Although the test generated a high clock of 400Mhz, negative slacks occurred and 200MHz or higher was judged to be difficult.
The system you are planning to develop will attempt to synchronize the DATA by generating a clock of 500 MHz on the FPGA. In the Cyclone V catalog, the main base clk was 400 MHz, so I made 400 MHz, but the limited Fmax was synthesized to 230 MHz. Therefore, we are finding a new FPGA product line because it is judged that it cannot be used with the FPGA currently in use.
I'm guessing that the Cyclone 10 or Stratix family (V or 10) is suitable, but I can't find an exact basis, so I'm posting on the forum.
The number of FPGA pins we are using is about 130, and the amount of LE used is as follows. And within the FPGA, CPU is not being used and there is no future plan.
Q1. Do you have a separate IO Port & Pin for High Speed?
Q2. Do you have any resources or parameters to check regarding PLL CLK speed on the Product Catalog or Datasheet?
(If you look at pic1 Stratix Datasheet, pic2 FPGA Product Catalog, where is it related to Clock Speed?)
Q3. I know how to configure the source can change the Restricted Fmax (Negative Slack), but do you have any official solutions and guidelines?
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with the findings.
Thank you for your patience.
Good day. For your question number 1 & 2, please refer to the following Datasheet on page 46 for High-Speed I/O Specifications, and page 40 for the PLL Specifications:
As regards restricted fmax, you cannot ignore the restricted fmax, it is the restricted performance that can be done based on your design. If you had a register in the DSP block, the restricted fmax will depend on the DSP block. If you assert a higher frequencies towards the restricted fmax, it will end up in violation within the DSP block to the output register.
This seems a device limitation, perhaps you may have to use a better performance device. Refer to the related link below:
Hope this can help.
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1. Is The fastest clock that can be made with ALTPLL is 40 pages of -c7 grade refers to the peripheral clock (155Mhz(b))? We receive a 40MHz clock from the outside and put it in ALTPLL INPUT. If I can use the clock of PLL OUT to 550 MHz(a), what am I missing?
What is The max of the fastest clock that I think can be made with ALTPLL is one of a, b, a, b, c, d, e?
2. I learned about ALTLVDS by looking carefully at the datasheet 46 page you showed me.
We asked because we wanted to control dac over 500 Msps. Can I control the 16-bit data bus at a high speed if I use ALTLVDS before that? According to DATASHEET, it was able to produce an OUTPUT of 400 MHz.
I'm looking for CYCLONE's LVDS EXAMPLE.
I found the link above, but I couldn't find the EXAMPLE FILE. I'm just downloading the PDF file and studying it.
Thanks to you, I'm learning a lot for you.