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I hope to use a Cyclone 10 GX device to generate and transmit data at 1.434 Gbps (see my post https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593). The output logic standard is diff SSTL-12. I cannot use LVDS because its common mode voltage is incompatible with my receiver, which is an ASIC. Another post (https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434-Gbps/m-p/1287593) states that the LVDS SERDES IP supports only LVDS. How can I transmit data at 1.434 in diff SSTL-12? Is there other SERDES IP that supports SSTL? Thanks.
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Have anyone used Cyclone 10 GX general purpose IO pins to transmit data at 1.434 Gbps? Have any experts viewed my post? Could you please share the experience? Thanks.
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Hello,
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Dear AminT_Intel,
Thank you for your reply. What is the highest data rate I can achieve with Cyclone 10 GX general purpose I/O pins in diff SSTL-12 standard and how can I achieve that data rate?
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Hello,
My previous answer will also be applied to this question. You can refer to these two documents for your design guidelines:
1. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
Thank you.
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We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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