I hope to use a Cyclone 10 GX device to generate and transmit data at 1.434 Gbps (see my post https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434...). The output logic standard is diff SSTL-12. I cannot use LVDS because its common mode voltage is incompatible with my receiver, which is an ASIC. Another post (https://community.intel.com/t5/Programmable-Devices/Does-Cyclone-10-GX-general-purpose-support-1-434...) states that the LVDS SERDES IP supports only LVDS. How can I transmit data at 1.434 in diff SSTL-12? Is there other SERDES IP that supports SSTL? Thanks.
My previous answer will also be applied to this question. You can refer to these two documents for your design guidelines:
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