How do I use the ALTLVDS_RX megafunction with 12-bit

[Altera_Forum]

Hi, 

 I am trying to connect 4 channel 12 bit LVDS ADC to Cyclone V, the megafunction ALTLVDS_RX support only 10 deserialization factor, this link (http://altera.info/support/kdb/solutions/rd07182013_904.html)suggest using two ALTLVDS_RX with 6 deserialization factor and then construct the 12 bit word, however it is not clear for me how I can do it. I already opened a ticket in Altera mysupport, but they did not give me a helpful answer. Can somebody please explain to me how to do it!

[Altera_Forum]

I made some progress, but I am stuck with a strange error in Quartus!  

 whenever I connect the final output of LVDS signal to NIOS II, I got an error message No. 129001.......the strange thing is, if I removed the connection to NIOS II, this error disappear and the compilation finished successfully.  Please have a look to the attached picture for more details.  an advice is highly appreciated.

[Altera_Forum]

Hi, 

I'm having the same problem. I have a serial datastream of 12 bit or each value. I need to make it parallel. Altera says use ALTLVDS_RX with des-factor of 6 and do it two times. But how?  Regards.    --- Quote Start ---  I made some progress, but I am stuck with a strange error in Quartus!   whenever I connect the final output of LVDS signal to NIOS II, I got an error message No. 129001.......the strange thing is, if I removed the connection to NIOS II, this error disappear and the compilation finished successfully.  Please have a look to the attached picture for more details.  an advice is highly appreciated.  --- Quote End ---  

[Altera_Forum]

Basically, set up the ALTLVDS megafunction to a 6:1 deserialization factor, then have a 12 bit register which is loaded with the data - in the first clock cycle of the 1/6th clock of the megafunction, load the first nibble (upper if MSB first, lower if LSB first), then in the second cycle load the other nibble. If you use it in external PLL mode, you can then set up the PLL to also generate a half clock (the 1/12th clock) which is has a phase such that it has a rising edge at the falling edge of the 1/6th clock to maximise the setup/hold between the 12bit packing register and the rest of your logic - have an extra 12bit register which is clocked by the 1/12th clock to synchronise it all.

[Altera_Forum]

But be aware to have some nibble_swap logic implemented. I think if you configure the LVDS_RX there is an option for the swapping as GPIO to the LVDS-Core...

[Altera_Forum]

Yeah, essentially for link training, you first use the bitslip feature of the ALTLVDS_RX core to align the bits within a nibble - you can do this by comparing the nibbles as they come in to both halves of your 12bit training word. Once you get a match with one or other half of your training word, then you look at the whole word, and if you find that your it doesn't match, you add in a 1 clock cycle delay to the nibble stream to flip them around (this can be done with a mux and a register stage).

[Altera_Forum]

I think the disadvantage is that the rx_out frequency is reduced by half, as it take 1 cycle for 1st 6bits, 1 cycle for 2nd 6bits and then flushed to the core as 12 bits.

[Altera_Forum]

The output data rate is *identical* to the incoming data rate - it goes from being 12X MHz @ 1bit to being 2X MHz @ 6bit to being 1X MHz @ 12bit. The data rate coming in is 12X Mbps to being 12*1X Mbps.