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Valued Contributor III
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How does one overcome limitation of altera clock control block inputs?

The altera clock control block allows one to switch between 2 PLL clocks. These clock control hard IP blocks are fixed to specific PLLs. 

 

Is it bad idea to use normal logic multiplexer only because of the potential of glitch at the clock output? 

 

What does one do if there are more than 2 clocks that are to be switched? The newer devices have PLLs with many more output clocks than can be controlled via a clock control block.
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Valued Contributor III
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It isn't recommended, but mux in logic can work fine. 

 

It's discussed a bit on page 737 (page 11-7) of https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qts_qii5v1.pdf 

 

I've used the module in the cookbook (page 16-4) https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/stx_cookbook.pdf 

 

It depends on your application, but I've also used reprogrammable cascaded PLL
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Valued Contributor III
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thanks, 

 

I shall be possibly translating this code to VHDL for the clock multiplexer. I wonder why this clock multiplexer given in page 16-4 Figure 16-7 does not exist as a megafunction. Anyway, I have a question, 

 

What does the text here mean? This is taken from the clock_mux.v 

 

// A LUT can glitch when multiple inputs slew  

// simultaneously (in theory indepently of the function).  

// Insert a hard LCELL to prevent the unrelated clocks 

// from appearing on the same LUT. 

 

wire [NUM_CLOCKS-1:0] gated_clks /* synthesis keep */; 

 

I do not see any "LCELL" or "Synthesis keep" anywhere in the code apart from these comments.
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Valued Contributor III
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--- Quote Start ---  

thanks, 

 

I shall be possibly translating this code to VHDL for the clock multiplexer. I wonder why this clock multiplexer given in page 16-4 Figure 16-7 does not exist as a megafunction. Anyway, I have a question, 

 

What does the text here mean? This is taken from the clock_mux.v 

 

// A LUT can glitch when multiple inputs slew  

// simultaneously (in theory indepently of the function).  

// Insert a hard LCELL to prevent the unrelated clocks 

// from appearing on the same LUT. 

 

wire [NUM_CLOCKS-1:0] gated_clks /* synthesis keep */

 

I do not see any "LCELL" or "Synthesis keep" anywhere in the code apart from these comments. 

--- Quote End ---  

 

 

There is a synthesis keep in the snippet you posted, assigned to the gated_clks. They're using the gated_clks to put the 'AND' operation for each clock into one LUT, and then OR'ing those results in another. 

 

The comment and the descriptive text in the manual are describing that this is being done to avoid out_clk = (clk[0] & ena[0]) | (clk[1] & ena[1]) all ending up in a single LUT. 

 

At least, that is my understanding. 

 

If you want to understand it better, my suggestion would be to just take that block in isolation and examine how it maps to the hardware both with and without the 'synthesis keep' shown.
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