How many clock cycle latency for 32 bit Integer Multiplication in Altera Stratix V?

[Altera_Forum]

Hi  

 Since I am developing a hardware in verilog for high frequency application using Altera Stratix FPGA, and involves 32 bit integer multiplication. The application that I am designing needs the result of the multiplication in one clock cycle.   Question: Will I get the resultant product in one clock cycle?  I referred the Stratix V handbook and it says that a DSP module can handle   : One 27*27 multiplication  : Two 18*18 multiplication  : Three 9*9 multiplication  So from the above information, two 2 DSP blocks are required for parallel multiplication and subsequent summing up. But can this be done in a clock cycle   in Stratix V(Assuming that I am working at 100 - 200 MHz internal clock)   Thanks in advance  Jeebu Jacob Thomas

[Altera_Forum]

Stratix V has support for one independent 32x32 multiplication using 2 cascaded DSP blocks (internally routed). Should be able to achieve 200MHz easily for one clock cycle operation. 

 https://www.altera.com/products/fpga/features/dsp/stratix-v-dsp-block.html

[Altera_Forum]

Why not write some proof of concept code and run it through timequest?

[Altera_Forum]

--- Quote Start ---  Why not write some proof of concept code and run it through timequest?  --- Quote End ---    Hi Tricky, Thanks for the quick reply. We dont have a quartus tool to check through timequest yet. Quartus Evaluation version wont support Stratix V. We have just given order for buying the same.  Thanks again  Cheers Jeebu

[Altera_Forum]

Thanks a lot mikedsouze. 

 Cheers  Jeebu