How many lanes of PCIe does the 10CX085 in F672 package support?

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According to the Cyclone 10 GX Product Table, the 10CX085  supports PCIe Gen2 x4 as long as it isn't in the U484 package (see footnote 4).

However, when I look at the channel pin placement for PCIe x4 (Figure 23), it looks like x4 requires two transceiver banks, <txvr_block_N> and <txvr_block_N+1>. For example GXBL1C (the N) and GXBL1D (the N+1).

Moreover, in that same document in Figure 17, the 6-transceiver 10CX085 only has a single transceiver block (GXBL1D). Note 1 on Figure 17 also says "only CH5 and CH4 support PCIe Hard IP block with CvP capabilities." However, I'm a bit unclear what this note means...

Does this mean if you don't enable CvP then you can use all four lanes, or does it mean that since 6 transceiver devices only have one hard-IP which happens to support CvP, then you can only use 2 lanes no matter what, regardless of whether or not CvP is enabled?

If the latter, this seems to contradict the fact that the Cyclone 10 GX Product Table says that 10CX085 only don't support four lanes in the U484 package.

[wchiah · Accepted solution]

Hi,

If referring to Intel® Cyclone® 10 GX Device Overview document on page 15/22

https://www.intel.com/content/www/us/en/docs/programmable/683485/current/device-overview.html

• It mentions that " For the PCIe hard IP, only x2 lane configuration is available for the U484 package of the
  10CX085, 10CX105, 10CX150, and 10CX220 devices, and the F672 package of the 10CX085
  device. "
• 6 transceivers but it only supports up to PCIe x2 lanes.

Hope this is clarified, let me know if this is helpful.

Regards,

WeiChuan_C_Intel