How read data file in a testbench

Altera_Forum · ‎10-17-2009

Hi all:

Im trying to do my testbench, i want read the inputs from a .txt file and write the outputs to a .txt file

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_textio.all;

entity testUnidadALULog is

end;

architecture test of testUnidadALULog is

COMPONENT UnidadALULog is

port(

DatoA : in std_logic_vector (31 downto 0);

DatoB : in std_logic_vector (31 downto 0);

Operacion : in std_logic; --- 1 para Mulltiplicacion 0 para Division

AUXDATO_A, AUXDATO_B : out std_logic_vector (35 downto 0);

AUXSUMA : out std_logic_vector (36 downto 0);

AUXRESTA : out std_logic_vector (36 downto 0);

AUXselector: out std_logic_vector (36 downto 0);

Resultado_Entero : out std_logic_vector (63 downto 0)

);

end component;

signal PruDatoA, PruDatoB : std_logic_vector (31 downto 0);

signal PruOperacion : std_logic;

signal PruAUXDATO_A, PruAUXDATO_B: std_logic_vector (35 downto 0);

signal PruAUXSUMA, PruAUXRESTA: std_logic_vector (36 downto 0);

signal PruAUXselector: std_logic_vector (36 downto 0);

signal PruResultado_Entero: std_logic_vector (63 downto 0);

begin

Pruebas : UnidadALULog port map

(

DatoA => PruDatoA,

DatoB => PruDatoB,

Operacion => PruOperacion,

AUXDATO_A => PruAUXDATO_A,

AUXDATO_B => PruAUXDATO_B,

AUXSUMA => PruAUXSUMA,

AUXRESTA => PruAUXRESTA,

AUXselector => PruAUXselector,

Resultado_Entero => PruResultado_Entero

);

verificar : process

file datosin: TEXT open read_mode is "pruebasin.txt";

file datosout: TEXT open write_mode is "pruebasout.txt";

variable linea: line;

variable vDatoA, vDatoB :std_logic_vector(31 DOWNTO 0);

variable vOperacion: std_logic;

begin

while not endfile(datosin) loop

readline(datosin,linea);

read(linea,vDatoA);

read(linea,vDatoB);

read(linea,vOperacion);

PruDatoA <= vDatoA;

PruDatoB <= vDatoB;

PruOperacio <= vOperacion;

wait for 200 ns;

write(linea,PruAUXDATO_A);

write(linea, string'(" "));

write(linea,PruAUXDATO_A);

write(linea, string'(" "));

write(linea,PruAUXSUMA);

write(linea, string'(" "));

write(linea,PruAUXRESTA);

write(linea, string'(" "));

write(linea,PruAUXselector);

write(linea, string'(" "));

write(linea,PruResultado_Entero);

writeline(datosout,linea);

wait for 350 ns;

end loop;

wait;

end process verificar;

end test;

but when I comile testUnidadALULog.vhd in ModelSim program I have 2 Errors

# Unknown identifier text.

# File declaration must have a subtype indication that is a file type

do you know how what I have to do???

Thanks!!!!!!!!!!!!!!!1

Altera_Forum · ‎10-19-2009

you need to include the library std.textio.all aswell. std_logic_textio is just to get the std_logic/std_logic_vector write functions. functions for string, integer, bit (ie all the base types) are in the std.textio package. It also contains the text file type.