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I was reading through this discussion: https://community.intel.com/t5/Programmable-Devices/Agilex-5-LUTs/td-p/1647817
It made me wonder, When configuring LUTs in Agilex 5 FPGAs using the carry chain, is there a way to achieve independent control over the F0-F3 outputs while maintaining optimal timing? Specifically, how do you avoid conflicts between equations in adjacent LUT pairs when customizing logic functions?
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On older chips, the delay really does ripple down the chain. However, on the Agilex 5, if you implement it in silicon, you'll notice that it starts bouncing ahead by cells, then half labs, and then full labs due to its built-in carry lookahead type circuitry. As a result, you won't see uniform delay steps on the sum outputs.
To achieve the desired pattern and performance, we recommend experimenting with hardware configurations to find the best fit for your needs. One effective approach is to switch from using carry chains to wire LUTs. For example:
VERILOG
wire [19:0] delay_line /* synthesis keep */;
assign delay_line = {delay_line[18:0], din};
wire dout = delay_line[19];
You can easily place this configuration using location assignments by dragging and dropping in the Chip Planner, allowing you to create any layout you prefer. Once you have a layout that works for you, you can then in mass-producing it.
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Anymore question on this?
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As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions

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