How to Infer a ROM's Contents from a file?

[ALane]

I'm trying to convert a Xilinx design onto a Cyclone V and am struggling with the Intel documentation on how to infer a ROM where its contents are provided by an external mif file​. Looking at the documentation this idea does not seem to be covered. (i.e. the examples all appear to generate the ROM contents within the hdl files)

Here is a snippet from the code I am trying to re-use:

impure function init_mem(mif_file_name : in string) return T_ROM_TYPE is

   file mif_file  : text open read_mode is mif_file_name;

   variable mif_line : line;

   variable temp_bv : std_logic_vector(G_DATA_WIDTH-1 downto 0);

   variable temp_mem : T_ROM_TYPE;

begin

   for i in T_ROM_TYPE'range loop

       readline(mif_file, mif_line);

       hread(mif_line, temp_bv);

       temp_mem(i) := temp_bv;

   end loop;

   return temp_mem;

end function;

-- ROM array constant

constant rom : T_ROM_TYPE := init_mem(G_ROM_INIT_DATA);

begin

-------------------------------------------------------------------------------

-- ROM read access control

-------------------------------------------------------------------------------

rom_cotrol_proc : process (CLK)  

  variable address : integer range 0 to ((2**G_ADDR_WIDTH)-1);

   begin                                                       

  if CLK'event and CLK = '1' then                             

   if IP_EN = '1' then 

   address := to_integer(unsigned(IP_ADDR((G_ADDR_WIDTH-1) downto 0))); 

   OP_DATA <= rom(address);     

   end if;                                                     

  end if;                                                     

   end process;                     

[Tricky]

Unfortunately, Quartus has been lacking the ability to infer the ram contents using textio for years - I raised an enhancement request on this 10 years ago - afaik this is still not possible!!!!

You can use the  ram_init_file  attribute to read the contents of a .mif file during synthesis, but it wont load it during simulation. The only way to load it during simulation is with an init function (like the one you posted - but this only would need to be removed from synthesis) or by using the altsyncram megafunction and specifying an init_file generic to the .mif file

[Abe · Accepted solution]

You could initialize the memory using MIF file or Intel HEX file. I would suggest you replace your ROM code with one of Intel's 1-port ROM Megafunctions. When you use the megafunctions, there's an option to initialize the memory using MIF or HEX files.

Migrating the small ROM/RAMs to using Intel megafunctions may help resolving such issues.

-Abraham

[ALane]

Thanks for the answers!

Looks like I'll try the mega function where I can at least setup the ROM dimensions/contents via generics.