How to Sim P-tile PCIe ST IP Core With modelsim in quartus19.3

[GDeXi]

Hi all

I want to Sim P-tile PCIe ST IP Core. and I read Example User guide that only have VCS simulation , When I run modelsim with example like before, i type the msim_setup.tcl and then ld_debug ,there are some mistake like below :

# Top level modules:

#   intel_pcie_bam_hwtcl

# End time: 14:41:19 on Dec 25,2019, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vlog 2019.2 Compiler 2019.04 Apr 17 2019

# Start time: 14:41:19 on Dec 25,2019

# vlog -reportprogress 300 -sv ../../../../ip/pcie_ed/pcie_ed_pio0/intel_pcie_pio_191/sim/intel_pcie_bam.sv -work intel_pcie_pio_191

# ** Error: (vlog-13069) ../../../../ip/pcie_ed/pcie_ed_pio0/intel_pcie_pio_191/sim/intel_pcie_bam.sv(42): syntax error in protected region.

#

# ** Error: ../../../../ip/pcie_ed/pcie_ed_pio0/intel_pcie_pio_191/sim/intel_pcie_bam.sv(42): (vlog-13205) Syntax error found in the scope following '<protected>'. Is there a missing '::'?

# End time: 14:41:19 on Dec 25,2019, Elapsed time: 0:00:00

# Errors: 3, Warnings: 0

# /opt/EDATools/Quartus19_3/modelsim_ase/linuxaloem/vlog failed.

please get some help, thanks a lot

[BoonT_Intel]

Hello Sir,

Unfortunately, for P-tile PCIe, currently it only support for VCS simulation only. Please use VCS if you want to run the simulation for P-tile PCIe. Thanks.

This is also covered in the user guide as you mentioned.