Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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How to calculate the delay from flop to pin in FPGA with constraints?



I have set min and max delay constraints for an output pin wrt an input clock.


set_min_delay -from input_clock -to [get_ports {output_pin}] 4

set_max_delay -from input_clock -to [get_ports {output_pin}] 13


I am analyzing the clock to output delay of the pin in multicorner analysis to know the delay for this signal from the last flop to output pin.

It shows a variation from 5.4 ns to 12.4ns across PVT(Slow to Fast process). But when I try to measure the clock to output delay on board by probing the input clock and output pin for a rising edge I see only a delay approx 5ns.


So I am doubtful whether my timing analysis is wrong.





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