How to check which FPGA is assembled on the pcb?

[Altera_Forum]

Hi all, 

I am using pcb designed for many various projects. On this pcb can be placed one of the following FPGA devices: 5CEBA4 or 5CEBA5 or 5CEBA7 or 5CEBA9. The device which will be assembled depends on the project. To configure FPGA, I am using external host (microprocessor), which sends programming data from external memory to FPGA. Because I can have various types of FPGA on the board I want to make sure that programming data stored in the memory is dedicated to the FPGA assembled on the board.  Is it possible to read part number of the device before microprocessor starts configuring it? I suppose I could use JTAG interface (btw. how, any hint?). But any other ways? Maybe there is another way to check if FPGA assembled on the board and programming data stored in external memory match? Of course microprocessor has to do that.  I know for which device, programming data was prepared, so the case is to know what FPGA is on the pcb.    And on the other hand what can happen if I send to FPGA on the pcb configuration program dedicated to another device?

[Altera_Forum]

JAM STAPL might be a good fit for your application. I believe the IDCODE.jam example they supply does basically what you're looking for.

[Altera_Forum]

--- Quote Start ---    Is it possible to read part number of the device before microprocessor starts configuring it?   --- Quote End ---    If you have JTAG connected to your processor, then that would be easiest. Its pretty easy to read the IDCODE or USERCODE via JTAG - you just bit-bang the JTAG TAP machine into the appropriate state and read out the data.    --- Quote Start ---   But any other ways? Maybe there is another way to check if FPGA assembled on the board and programming data stored in external memory match? Of course microprocessor has to do that.    --- Quote End ---   On designs that I can load different FPGAs I add 0402 stuff resistors across the BGA pads on the bottom side of the PCB (so that no routing is required). I then load different stuff resistors for the board revision, device type, and FPGA number (because I have multiple FPGAs).   Cheers, Dave

[Altera_Forum]

--- Quote Start ---  If you have JTAG connected to your processor, then that would be easiest. Its pretty easy to read the IDCODE or USERCODE via JTAG - you just bit-bang the JTAG TAP machine into the appropriate state and read out the data.  --- Quote End ---    But the IDCODE is not unique for each part. I don't know about the Cyclone V's mentioned, but when you use jtagconfig you see a list of candidates for the given ID:   02A030DD 5AGT(FD3H3|MD3G3)/5AGXBB3D4/..  029030DD 5SGXEA7H(1|2|2ES|3|3ES)/..

[Altera_Forum]

--- Quote Start ---  But the IDCODE is not unique for each part. I don't know about the Cyclone V's mentioned, but when you use jtagconfig you see a list of candidates for the given ID  --- Quote End ---    That's a good point actually. Someone at Altera has been screwing up and not changing the JTAG IDCODE on devices.  Though in this particular case, so long as the list of devices that can possibly be loaded on the PCB do not have duplicate IDCODEs, then reading the IDCODE could be used to determine which unique part was loaded. If however the IDCODEs are not unique, then a resistor stuff option that the microcontroller can read *BEFORE* the FPGA is configured would be needed. Although if the resistors were connected to FPGA pins, you could perform a boundary scan of the FPGA to read those pins, before configuring the device.  Cheers, Dave

[Altera_Forum]

Reading the serialnumber, resistors, MAC, or some other information where the FPGA kund can be derived is probably the best option unless the IDCODE is unique across the parts used and will be so for future versions of the product.

[Altera_Forum]

I think IDCODE is good enough to narrow down the capacity and flavor of device within a family, but it doesn't include device speed grade information or temperature range. 

 http://www.altera.com/literature/hb/cyclone-v/cv_52009.pdf  "the idcode is unique for each cyclone v device. use this code to identify the devices in a jtag chain."

[Altera_Forum]

Thanks for suggestions. 

 I have found document: jtag boundary-scan testing in cyclone v devices (http://www.altera.com/literature/hb/cyclone-v/cv_52009.pdf). Table 9-1 (page 1) shows that every Cyclone V device has unique IDCODE, so I think I can use it in my projects.    --- Quote Start ---  On designs that I can load different FPGAs I add 0402 stuff resistors across the BGA pads on the bottom side of the PCB (so that no routing is required). I then load different stuff resistors for the board revision, device type, and FPGA number (because I have multiple FPGAs).   --- Quote End ---      --- Quote Start ---   If however the IDCODEs are not unique, then a resistor stuff option that the microcontroller can read *BEFORE* the FPGA is configured would be needed. Although if the resistors were connected to FPGA pins, you could perform a boundary scan of the FPGA to read those pins, before configuring the device.   --- Quote End ---    Dave, could you explain more details? Because it is not clear for me. Between which pads do you add resistors? How are they read by uP?

[Altera_Forum]

--- Quote Start ---   Dave, could you explain more details? Because it is not clear for me. Between which pads do you add resistors? How are they read by uP?  --- Quote End ---    Go take a look at this board:  http://www.ovro.caltech.edu/~dwh/carma_board/  Click on the PDF for the schematic:  http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf  p50: You will see the SYS-FPGA ID code resistors  p57: You will see the DATA-FPGA ID code resistors  What does this look like on an FPGA? Look at this image;  https://www.alteraforum.com/forum/attachment.php?attachmentid=8760   The blue components between BGA pins are resistors. The other components are decoupling capacitors.  The addition of the ID registers "costs nothing", since you can use I/O pads that might otherwise be difficult to get to, eg., they're near the center of the BGA.  In my system, the SYS-ID stuff resistors tell the PowerPC processor which DATA-FPGAs are loaded; Stratix II EP2S90 or EP2S130 devices. The SYS-FPGA then configures the four DATA-FPGAs. The pinouts of those four FPGAs are almost identical. The ID pins are in the same location, as are the inter-FPGA buses. To ensure there is no possibility of bus conflict, each configuration reads the DATA-FPGA-ID stuff resistors and checks that the value matches what they expect, eg., the configurations for DATA-FPGA#0, 1, 2, 3 expect IDs of# 0, 1, 2, 3. If the IDs do not match, then the inter-FPGA buses are not enabled. For a 'basic' configuration, I can load the same design into all four FPGAs.  Cheers, Dave

[Altera_Forum]

Thanks for your explanation Dave.