Component Declaration

[Altera_Forum]

Hey people, I have a simple question that I can't find an answer to on the web. I have a code for a simple vga test which is split in three sections. I can't figure out a way to connect the three of them together. So what do I need to do in Quartus II to make this happen, I mean how to compile everything as whole code? I posted part of the code if that's ok. 

 ------Part one------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity VGAdrive is port(  clk, reset: in std_logic;  hsync, vsync: out std_logic;  video_on, p_tick: out std_logic;  pixel_x, pixel_y: out std_logic_vector(9 downto 0)  );  end VGAdrive;  architecture arch of VGAdrive is  ... end arch; ------Part one-------  ------Part two-------  library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity pong_graph_st is port(  video_on: in std_logic;  pixel_x,pixel_y: in std_logic_vector(9 downto 0);  graph_rgb: out std_logic_vector(2 downto 0)  ); end pong_graph_st;  architecture sq_ball_arch of pong_graph_st is  ..... end sq_ball_arch;  ------Part two-------  ------Part three------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;   entity pong_top_st is port (  clk, reset : in std_logic ;  hsync, vsync : out std_logic;  rgb: out std_logic_vector (2 downto 0) ); end pong_top_st;  architecture arch of pong_top_st is  signal pixel_x, pixel_y: std_logic_vector (9 downto 0 );  signal video_on, pixel_tick: std_logic;  signal rgb_reg, rgb_next: std_logic_vector ( 2 downto 0);  begin  --instantiate VGA sync  vga_sync_unit: entity work.VGAdrive  port map(clk=>clk, reset=>reset,  video_on => video_on, p_tick => pixel_tick,  hsync => hsync, vsync => vsync,  pixel_x => pixel_x, pixel_y => pixel_y);  --instantiate graphic generator  pong_grf_st_unit: entity work.pong_graph_st(sq_ball_arch)  port map (video_on => video_on,  pixel_x => pixel_x, pixel_y => pixel_y,  graph_rgb => rgb_next);  --rgb buffer  process (clk)  begin  if (rising_edge(clk)) then  if (pixel_tick ='1') then  rgb_reg <= rgb_next;  end if;  end if; end process; rgb <= rgb_reg; end arch;    ------Part three-------

[Altera_Forum]

I dont think you need to connect them together, it looks like pong_top_st is the top level.

[Altera_Forum]

Hi, yes it is but how can I make it work in quartus II ? Are these the correct steps: 

1. New project wizard 2. Make directory 3. Select device 4. New VHDL file 5. Write all the code in one VHDL file and compile

[Altera_Forum]

You can use separate files. I usually have separate files for all entities and packages.  

Next you tell Quartus which is your top-level entity (right click on file in project navigator, or via settings). If your code is correct it should compile. But are you getting any errors that you ask how this works?

[Altera_Forum]

No the code is error free. I did a project named VGAdrive , specified directory and device, created a new VHDL file and wrote all the code in it. But even though there are three different entities in one file, Quartus is only compiling the VGAdrive part leaving the other two out apparently. I know I'm doing something wrong cause the top level specifies 2 inputs and 3 outputs but what I'm getting is the VGAdrive inputs and outputs in the pin assignment. So my question is, I have two components and a top level. What are the steps in quartus for the three parts to work together. 

 So I know what you're trying to say PietervanderStar but I don't know how to do it and I can't find like a step by step thing on the web.

[Altera_Forum]

assignments->settings 

tab: general

[Altera_Forum]

PietervanderStar, you're a HERO. Cheers buddy.

[Altera_Forum]

You're welcome.