How to communicate with I2S block that works at much slower frequency to communicate

[Altera_Forum]

I am going to write an I2S block soon (I must write my own), one issue I just realized that I have is that the data output must be synchronized with the MCLK clock sent to the DAC. This master clock has very specific very frequency depending on the sampling rate of the audio data being sent to the DAC. A table is present in data sheet of the audio DAC CS4334 on page 13. 

  Therefore, if I want to interface with this I2S block that be part of the FPGA design, I need a mechanism to deal with the different clock domains. Signals shall be transmitted both ways, from the I2S block to rest of the design and rest of the design to the I2S block.   What is the correct way to approach this problem? Certainly without correct approach the design shall not work. Also, is it ok for me to generate a clock from the FPGA internal PLL and feed it to the DAC?

[Altera_Forum]

There are many tutorials for this. Search for "clock domain crossing". For this, I'd use a pair of FIFOs, one for each direction. 

 One issue that burned me on my first I2S project, the samples are signed integers. I couldn't figure out why I was getting very low audio levels with my square wave test signal (0x0000-0x1111"