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Altera_Forum
Honored Contributor I
1,233 Views

How to configure ArriaV FPGA with GHRD RBF via QSPI

Hello, 

 

 

I'm currently stuck with an issue where the Arria V fail to program/configure from HPS QSPI. I'm using Arria V SOC DevKit and the files in Altera 15.1 GHRD. The preloader and u-boot are working. 

 

Under default board settings, it can successfully load the Linux system if booted with the default accompanying SD card. 

 

 

Setup 

 

Since we are using QSPI, I can't use the released binaries since its for SD. I followed the following webpage to create my preloader and u-boot and get them both working: 

 

https://rocketboards.org/foswiki/documentation/gsrd131qspiboot 

https://rocketboards.org/foswiki/documentation/gsrd131preloader 

 

I tried to generate Linux kernel and minimal FS from below page: 

https://rocketboards.org/foswiki/documentation/gsrd131gettingstartedyocto 

 

but the bitbake procedure always fail, even if I did download all dependencies. Not sure if the yocto folder is at fault here for being too outdated. So I just created a baremetal FW that u-boot can pass control to and I will be attaching to in my DS-5 debugger. I used the supplied RBF file in GHRD folder (around ~6MB++). 

 

I run the following commands in u-boot which are essentially the contents of bootcmd u-boot variable: 

run qspifpga 

run bridge_enable_handoff 

Then I check registers from FPGA 

 

 

Problem/Result 

 

The problem is, it seems the FPGA didn't configure successfully and so we can't access its registers. The test register I accessed in u-boot to test this is 0xc0000000 and everytime I did, the board just hangs up. Even if I do check that address in baremetal FW, it also hangs up. That to me means I can't use the FPGA correctly. 

 

My suspicion is that it has something to do with a message "altera_load: Failed with error code -4". It says timeout error, but I don't know why it happens when I followed all the procedure. Checking the values of CONF_DONE and nSTATUS reveals 0 and 1 respectively. This is after the "fpga load ..." cmd inside the "run qspifpga" cmd in u-boot. 

 

Other things I played with: 

Changed MSEL switch between for uncompressed and compressed (mentioned in the above website) 

- No good 

Tried to attach with u-boot with its debug symbols - No good since symbols didn't load correctly. 

Tried to configure FPGA via preloader - no good 

Tried to attach to that FPGA-configuring preloader in debugger - polls indefinitely in fpga_program_poll_cd meaning it is stuck waiting for CONF_DONE asserting infinitely till watchdog kicks in. 

 

How do I solve this, especially the altera_load msg above?
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2 Replies
Altera_Forum
Honored Contributor I
80 Views

OK, so there was an improvement here. I changed the mSEL switch to 00110 and it worked. I can now access the FPGA registers which was not possible before. 00100 MSEL settings also work. 

 

My next problem is that a slightly modified GHRD rbf (default GHRD rbf just added with LED blinker) is not working, even if I played with MSEL settings. Its .sof equivalent works, but what's keeping the rbf from working properly. If we can solve this, we can be more confident of doing our ArriiaV-based project.
Altera_Forum
Honored Contributor I
80 Views

How did you generate the rbf file? When using the convert programming filea tool, I found out that the "mode" setting is very important. Leaving it to "1-bit passive serial" doesn't work, but putting it to "passive parallel x16" works in both 16-bit and 32-bit MSEL settings. The compression can be enabled or disabled when you add the sof file and click on properties. It must also correspond to your MSEL settings. 

If you have Quartus automatically generate the .rbf file when it compiles the project, the options can be found in the "Device" item in "Assignments" menu, "Device and Pin Options" and "Configuration".
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