How to control the I/O pins during power up or configration

[Altera_Forum]

Hi everyone, 

I'm working on a project which will use fpga as inteface for emif of TI DSP. I will use cyclone or cyclone II as this inteface chip. But some FPGA's I/O pins should remain Low during fpga's power-up and configration according to this project.  Now , How can i control the I/O pins during power up or configration? Can I use pull down resistor? If i can use the pull down resistor, which parameter for this resistor? 1kΩ or 10kΩ?  Thanks, Sonic

[Altera_Forum]

Hello, 

 this can be achieved by a resistor. You have to consider minimum weak pullup resistance from datasheet and maximum VIL level for the input. I recently calculated 2.2k maximum pulldown resistance for a similar problem, 1k should work under all conditions without further calculations.  Regards, Frank

[Altera_Forum]

Hi, Frank 

 Thanks for your help.  According to cyclone II's DC Characteristics, the Minimum pullup resistance before and during configuration is 10kΩ (when VCCIO=3.3V) , and the maximum VIL level for Ti DSP is 0.8V. which resistance is proper?  Thanks, Sonic

[Altera_Forum]

That's a voltage divider you can calculate yourself. If you want to achieve TTL maximum VOL of 0.4V, not only 0.8V maximum VIL, then you need 1.3k or 1k rounded down. 1k pulldown guarantees maximum power-up level of 0.3V.

[Altera_Forum]

Hi, Frank 

Thanks for your help.  If I want the FPGA's I/O pins remain High during fpga's power-up and configration, should I use the pull up resistor and which parameter for this resistor?

[Altera_Forum]

This is achieved by default pin behavior as long as load pins won't sink current. But interference supression or supply voltage sequencing issues can require additional pullups in some cases.