I have two simple 5-input and 3-input functions in Verilog.Function 1: 3:1 Multiplexer input a,b,c; input [1:0] s1; output wire east; Function 2 : 2:1 Multiplexer input d,e; input s2; //sel line output wire south; Multiplexers are written with Case statements. When I try so synthesize it in Altera with Aria - 10 FPGA selected. This gets mapped to 2-ALMs. But I saw in datasheets that only 1-ALM is required to implement a 5-input and 3-input functions. How do I force the ALM to map this logic in one Cell.
What is your goal here? Are you concerned about resource usage? Yes, the compiler should be able to do what you are referring to. Are you looking at the Fitter compilation report or just synthesis? If it's just synthesis, it's not optimized yet for actual resource use.
Can you post the code you used to generate the two muxes? The Mux2/Mux3 primitives do not exist in the tool. You will have to use two assign statements to generate the mux. I tried the same code as you've posted and got only 1 ALM usage.Fitter Status Successful - Sat Jun 23 23:54:10 2018 Quartus Prime Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition Revision Name test_alm Top-level Entity Name test_alm Family Arria 10 Device 10AX115H1F34I1SG Timing Models Final Logic utilization (in ALMs) 1 / 427,200 ( < 1 % ) Total registers 0 Total pins 8 / 618 ( 1 % ) Total virtual pins 0 Total block memory bits 0 / 55,562,240 ( 0 % ) Total RAM Blocks 0 / 2,713 ( 0 % ) Total DSP Blocks 0 / 1,518 ( 0 % ) Total HSSI RX channels 0 / 24 ( 0 % )
Hi,Thanks for the help. There was a (*KEEP*) attribute in my multiplexer code which was leading to generating 2 ALMs. As I removed the attribute, the compiler is using 1 ALM.