How to disable lvds output in arria 10 chip dynamically?

[lambert_yu]

Hi, all

   fpga: arria 10

   quartus II: 18.0 standard

  I have requirement  for the lvds ip, when I have no data output, I need to disable lvds pin dynamically. So I add below design:

    tx_serdes tx_serdes_inst(

   .inclk (clk),

  .rst  (rst),

  .data (data),

  .tx_coreclock(usr_clk),

 .data_o (data_lvds) //io standard : "lvds"

);

assign data_o = oe ? data_lvds : 1'bz;

From this Why do I see functional errors in hardware when implementing... (intel.com), I know there's bug and from this information, I don't know if there's chance to disable the lvds output?

 If not, how could disable lvds output dynamically? If yes, is there chance to modify this issue in quartus II 18.0? Or I need to use the quartus 22.0 or later version?

BRs,

Lambert

[FvM · Accepted solution]

LVDS IO-standard has no tri-state feature, independent of FPGA series or Quartus version. You can refer to BLVDS (bus LVDS) if it's fast enough. On Arria 10, there's no BLVDS choice available, you'll use differential SSTL instead.

See: https://www.intel.com/content/www/us/en/docs/programmable/683803/current/implementing-bus-lvds-interface-in-supported.html

[lambert_yu]

Hi FvM,

   Thanks for your help.

   I found that there's one required choice (Use pseudo-differential buffer) in altera gpio ip. So if I use SSTL IO standard instead of POD io standard, there's no error, right?

BRs,

Lambert

[AqidAyman_Intel]

Based on the Application note, you can use Differential SSTL-I8 Class I and II if you want to implement BLVDS interface. With the BLVDS, the output buffer and input buffer can share with the same I/O pins, and you need OE signal to disable the LVDS output buffer when not sending signals.

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683803/current/blvds-technology-in-devices.html

[lambert_yu]

Hi, Aqid

    I tried this solution, and I found that when I set the oe to low, there's no data on the bus.  I used two diff pair to do this test. I found that there's one pad which input has random 0->1 or 1-> 0 toggle, and anothe didn't have when these two pad are all input and diff bus was not driven. I don't know why, could you help proide some information for this?

    my design: arria 10 (10ax115n3f45i2sg)

   one diff pair :  (in 2j bank, which use the reference clock from its dedicated clk pin)

    pll instance1();

   gpio instance1(); (simple register mode)

  another diff pair: (in 2h bank, which use the reference clock from its dedicated clk pin)

  pll instance2();

   gpio instance2(); (simple register mode)

   pattern : 0101010...

  connection : these two diff pairs connected directly.

BRs,

Lambert

[FvM]

Hi,
not sure what you are trying to achieve. Seeing no output with OE=0 (output inactive) is expectable. A receiver on the bus might however read arbitary data (= noise) when no peer is driving the bus. You can try bias resistors as used in RS-485 to enforce a defined state of undriven bus.

[lambert_yu]

Hi, FvM

   Now I am just for testing one differential pair could used be either input or output when use bus lvds solution. And now just we have limited hardware resource, we connect two differential pairs to test the solution. And we didn't setup the external termination part (without series terminations). So I think your opinion is reasonable (arbitary data (= noise)). Thanks!

BRs,

Lambert

[AqidAyman_Intel]

Hi Lambert,

Do you have any update on what being asked by @FvM?

Do you still need help on this?

Regards,

Aqid

[lambert_yu]

Hi, Aqid

    Sorry for the delayed response.

    Current I think bus lvds solution is okay for our design. We will test again when we get the newest hardware design. Thanks.

BRs,

Lambert

[AqidAyman_Intel]

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