How to do the timing constraint?

[Altera_Forum]

Hi, 

 Refer to the appendix,how to do the timing constraint with the both FPGA to reach the expected timing?  for the set_input_delay and the set_output_delay,what time relation does it tell the FPGA?

[Altera_Forum]

Yep. 

 There are two steps to this. First, you need to set constraints that ensure that your design will work if they are met. Second, when the constraints aren't met, you need to modify your design. Ie, use the PLL to shift a clock phase. And of course, it's not always possible to meet the constraints.  In most applications, the I/O constrains are fixed by the system outside your FPGA,  In this particular case, you have two FPGAs and thus you also have the freedom to shift constraints around to make them easier to meet.

[Altera_Forum]

Hello. 

I have encountered problems on the following timing constraint. The case is draw in the attachment. I do timing constraint as follows. creat_generated_clock -add -name {SysClk} -source [get_pins {*|inclk[0]}] [get_pins {*|clk[0]}] set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[0]}] [get_ports {D[*]}] -add_delay set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[1]}] [get_ports {D[*]}] -add_delay set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[2]}] [get_ports {D[*]}] -add_delay set_input_delay -clock [get_clocks {SysClk}] -max tOA -reference_pin [get_ports {A[3]}] [get_ports {D[*]}] -add_delay But the timing constraint is ignored for the reason as said in the tool. "the A[0] is not clocked by the clock specified in set_input_delay/set_out_delay -clock options."(I can remember only these,maybe something is missing.)  So,why the warning occurs?And how to do timing constraint at this case?